| Day 3 - Thursday, January 7th, 2010 |
| 09:00 |
09:45 |
Chair: Navakant Bhat, IISc Bangalore |
|
|
|
Track A |
Track B |
Track C |
Edu. Forum |
| 09:50 |
11:05 |
Session A7: Scan Testing
Chair: Erik Larsson, Linkoping University. |
Session B7: Nanoelectronic Design
Chair: Bernard Courtois, CNRS Grenoble. |
Session C7:
Circuit Design I
Chair: Prakash Easwaran, Cosmic Circuits. |
|
| 09:50 |
10:15 |
A7.1: A Unified Solution to Scan Test Volume, Time, and Power Minimization.
S.Seth, University of Nebraska-Lincoln,Z.Chen, D.Xiang, Tsinghua University,B.Bhattacharya, ISI Kolkata |
B7.1: Identifying the Bottlenecks to the RF performance of FinFETs.
V. Subramanian,IBM,
B. Parvais, A.Mercha, M. Dehan, G.Groeseneken,
S. Decoutere, IMEC, Leuven,
W. Sansen,
KU Leuven |
C7.1: Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product.
R. Dutta, T. K Bhattacharyya, IIT Kharagpur; X. Gao, E. A. M. Klumperink, University of Twente |
Education Forum Details |
| 10:15 |
10:40 |
A7.2: Hamming Distance Based Reordering and Column-wise Bit Stuffing with Difference Vector: A Better Scheme for Test Data Compression with Run Length Based Code.
U.Mehta, Nirma University, Ahmedabad,
K.Dasgupta, ISRO Ahmedabad, N.Devashrayee, Nirma University, Ahmedabad |
B7.2: Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors.
V.Saripalli, V.Narayanan, S.Datta, Penn State University |
C7.2: 23.97GHz CMOS Distributed Voltage Controlled Oscillators with Inverter Gain Cells and Frequency Tuning by Body Bias and MOS Varactors Concurrently.
K. Bhattacharyya, IIT Mumbai |
Education Forum Details |
| 10:40 |
11:05 |
A7.3: On Minimization of Test Aplication Time for RAS.
R.Adiga, A.Gandhi, V.Singh, IISc Bangalore,K.Saluja, University of Wisconsin-Madison,H.Fujiwara, Nara Institute of Science and Technology,
A.Singh, Auburn University |
B7.3: Clocking-based Coplanar Wire Crossing Scheme for QCA.
R.Devadoss, K.Paul, M.Balakrishnan, IIT Delhi |
C7.3: Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs
H.Thapliyal, N.Ranganathan, University of South Florida, Tampa |
Education Forum Details |
| 11:05 |
11:30 |
Break |
| 11:30 |
12:45 |
Session A8:
Fault Models and Test Generation
Chair: Nagesh Tamarapalli, AMD |
Session B8:
Secure / Reversible Computing
Chair: Vijaykrishnan Narayanan, Penn State University. |
Session C8:
Circuit Design II
Chair: Jagadesh Kumar, IIT Delhi |
|
| 11:30 |
11:55 |
A8.1: Identifying Tests for Logic Fault Models Involving Subsets of Lines Without Fault Enumeration.
I.Pomeranz, Purdue University;
S.Reddy, University of Iowa |
B8.1: RTL Hardware IP Protection Using Key-Based Control and Data Flow Obfuscation.
R.Chakraborty, S.Bhunia, Case Western Reserve University |
C8.1: 4 GHz 130nm Low Voltage PLL Based On Self Biased Technique.
V.Viswam, B.Viswanathan, Kulanthaivelu R., J.Vettickatt, R.Nair, L.Chandran, Network Systems and Technologies |
Education Forum Details |
| 11:55 |
12:20 |
A8.2: Impact of Temperature on Test Quality.
L.Jagan, IIT Chennai, C.Hora, B.Kruseman, S.Eichenberger, A.Majhi, NXP Semiconductors,
V. Kamakoti, IIT Chennai |
B8.2: Pinpointing Cache Timing Attacks on AES.
C.Rebeiro, M.Mondal, D.Mukhopadhyay, IIT Kharagpur |
C8.2: An Improved High Resolution CMOS Timing Generator Using Array of Digital Delay Lock Loops.
S.Balaji, Anna University, Chennai,
V.B.Chandratre, BARC Mumbai |
Education Forum Details |
| 12:20 |
12:45 |
A8.3: Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults.
S.Hasan, A.Palit, W.Anheier, University of Bremen |
B8.3: An Efficient Design of a Reversible Barrel Shifter.
I.Hashmi,George Mason University, Virginia; H.H.Babu, University of Dhaka. |
C8.3: Analog Circuit Design Methodologies to Improve Negative-Bias Temperature Instability Degradation.
A.Ghosh, University of Utah, Salt Lake City,
R.Franklin, University of Michigan,
Ann Arbor, R.Brown, University of Utah, Salt Lake City |
Education Forum Details |
| 12:45 |
13:45 |
Lunch |
| 13:45 |
14:30 |
Chair:
Ram Jonnavithula, Texas Instruments |
| 14:35 |
16:40 |
Session A9:
Microfluidics and Fault Diagnosis
Chair: Adit Singh, Auburn University. |
Session B9:
3D ICs and Network-on-chip
Chair: Anshul Kumar, IIT Delhi |
Session C9:
System Design and IP Protection
Chair: V.Kamakoti, IIT Chennai. |
|
| 14:35 |
15:20 |
|
|
|
Education Forum Details |
| 15:25 |
15:50 |
A9.2: Synchronization of Concurrently-Implemented Fluidic Operations in Pin-Constrained Digital Microfluidic Biochips.
Y.Zhao, Duke University; R.Sturmer, Advanced Liquid Logic; K.Chakrabarty, Duke University;
V.Pamula, Advanced Liquid Logic |
B9.2: Exploring Use of NoC for Reconfigurable Video Coding.
A.Patel, Cisco; H.Kapoor, IIT Guwahati |
C9.2: Functional Refinement: A Generic Methodology for Managing ESL Abstractions.
A.Thimmapuram, S.Abrar, NXP Semiconductors |
Education Forum Details |
| 15:50 |
16:15 |
A9.3: Output-Dependent Diagnostic Test Generation.
I.Pomeranz, Purdue University;
S.Reddy, University of Iowa |
B9.3: Design of NoC for SoC with Multiple Use Cases Requiring Guaranteed Performance.
G.Leary, K.Chatha, Arizona State University |
C9.3: A Unified Approach for IP Protection across Design Phases in a Packaged Chip.
D.Saha, S.Sur-Kolay, ISI Kolkata |
Education Forum Details |
| 16:15 |
16:40 |
A9.4: Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients.
S.Sindia, Analog Devices V.Singh, IISc Bangalore; V.Agrawal, Auburn University |
|
|
Education Forum Details |
| 16:40 |
17:00 |
Break |
| 17:00 |
18:00 |
|
|
|
Education Forum Details |
| End |
|
|
