VLSI Design 2010 VLSI Design 2010
VLSI Design 2010 VLSI Design 2010
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Schedule
Day 2 - Wednesday, January 6th, 2010
08:30 09:15 Technical Keynote 4 - Wally Rhines (Mentor Graphics)
Chair: Vasantha Erraguntla, Intel
    Track A Track B Track C Ind. Forum
09:20 10:35 Session A4: Verification and Formal Methods

Chair: Kaushik De, Synopsys Bangalore.
Session B4: Low-power Circuit Design

Chair: Nachiket Urdhwareshe, Softjin Bangalore.
Session C4: SOI

Chair: Santanu Mahapatra, IISc Bangalore.
 
09:20 09:45 A4.1: Synthesizability of Three Party Formal Specifications -- Does My controller See Enough?
A.Banerjee, Interra Systems
B4.1: A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM.
G.Thakral, S.Mohanty, D.Ghai, University of North Texas;
D.Pradhan University of Bristol
C4.1: RF SOI Switch FET Design and Modeling Tradeoffs for GSM Applications.
S.Parthasarathy, Y.Chauhan, A.Trivedi, M.Olsen, R.Groves, S.Sirohi, IBM
Industry Forum Details
09:45 10:10 A4.2: Coverage Management with Inline Assertions and Formal Test Points.
A.Hazra, P.Ghosh, P.Dasgupta, P.P.Chakrabarti, IIT Kharagpur
B4.2: Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control.
H.Xu, W-B.Jone, R.Vemuri, University of Cincinnati
C4.2: Modeling of High Frequency Noise in SOI.
M.Varadharajaperumal, S.Sirohi, S.Khandelwal, V.Subramanian, T.Ethirajan, IBM
Industry Forum Details
10:10 10:35 A4.3: Synchronized Generation of Directed Tests Using Satisfiability Solving.
X.Qin, M.Chen, P.Mishra, University of Florida, Gainesville.
B4.3: Inexact Decision Circuits: An Application to Hamming Weight Threshold Voting.
B.Rajaram, A.Ramachandran, S.Purini, G.Regeti, IIIT Hyderabad
C4.3: A New Hetero-material Stepped Gate SOI LDMOS for RF Power Amplifier Applications.
R.Sithanandam, M.J.Kumar, IIT Delhi
Industry Forum Details
10:35 11:00 Break
11:00 12:40 Session A5: Architectural Exploration and Design Closure

Chair: Padmini Gopalakrishnan, Xilinx Hyderabad.
Session B5:
Low-power Architecture


Chair: Saraju Mohanty, University of North Texas.
Session C5: Circuit Design and Modeling II

Chair: Swarup Bhunia, Case Western University.
 
11:00 11:25 A5.1: A Methodology for Power Aware High-Level Synthesis of Co-Processors from Software Algorithms.

S.Ahuja, S.Shukla,
A. Lakshminarayana, Virginia Tech, Blacksburg,
W.Zhang Cebatech
B5.1: Voltage-Frequency Planning for Thermal-Aware, Low Power Design of Regular 3D NoCs.

M.Arjomand, H.Sarbazi-Azad, Sharif University of Technology, Tehran
C5.1: Design Considerations for BEOL MIM Capacitor Modeling in RF CMOS Process.

B.Swaminathan, S.Parthasarathy, A.Sundaram, R.Groves, IBM
Industry Forum Details
11:25 11:50 A5.2: A Hierarchical Methodology for Word-Length Optimization of Signal Processing Systems.

K.Parashar, R.Rocher, D.Menard, O.Sentieys, University of Rennes-1, Lannion
B5.2: Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in
Real Time Systems.

W.Wang, P.Mishra, University of Florida, Gainesville.
C5.2: Modeling of RF-MEMS BAW Resonator.
A.Roy, University of Massachusetts Lowell;

B.Barber, Skyworks Solutions;
K.Prasad, University of Massachusetts Lowell
Industry Forum Details
11:50 12:15 A5.3: Post-assembly Timing Closure for Multi-million Gate Chips

S.Prasad, O.Levitsky, D.Liu, S.Srivastava, K.L.Cheong, D.Noice, Cadence Design Systems
B5.3: Rethinking Threshold Voltage Assignment in 3D Multicore Designs.

K.Chakraborty, S.Roy, Utah State University
C5.3: High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique.

K.Desai, V.Krishna, V.Khawshe, P.Venkatesan, R.Palwai, R.Nagulapalli, Rambus
Industry Forum Details
12:15 12:40 A5.4: Accelerating Synchronous Sequential Circuits Using an Adaptive Clock.

A.Mondal, Berkeley Design Automation;
P.P. Chakrabarti, P.Dasgupta, IIT Kharagpur
B5.4: Transition Inversion based Low Power Data Coding Scheme for Buffered Data Transfer.

A.Ramachandran, B.Rajaram, S.Purini, G.Regeti, IIIT Hyderabad
C5.4: A 6 bit 800MHz TIADC based on Successive Approximation in 65 nm Standard CMOS Process.

A. Salimath, DAIICT, Gandhinagar; C. Debnath, K. Chatterjee, ST Microelectronics; S. Mandal, DAIICT, Gandhinagar
Industry Forum Details
12:40 13:40 Lunch
13:40 14:25 Technical Keynote 5 - Prith Banerjee (HP Labs)
Chair: Anand Raghunathan, Purdue University
14:30 16:10 Session A6:
Design Challenges in Nano-CMOS


Chair: V.Vishwanathan, Texas Instruments Bangalore.
Session B6:
Scheduling and Operating Systems

Chair: Sanjiv Narayan, Calypto Systems New Delhi.
Session C6:
Novel Circuit Design


Chair: Dinesh Sharma, IIT Mumbai.
 
14:30 15:15 A6.1 / ET4: Embedded Tutorial: The New World Order at the Dawn of 22nm Era!
R. Puri, IBM
B6.1 / ET5: Embedded Tutorial: Front-End Design Flows for Systems on Chip.
A. Kumar, P. Panda, IIT Delhi
C6.1 / ET6: Embedded Tutorial: FinFET SRAM Design.
R.Joshi, K. Kim, R. Kanj, IBM
Industry Forum Details
15:20 15:45 A6.2: A P4VT (Power-Performance-Process-Parasitic-Voltage-Temperature) Aware Dual-VTh Nano-CMOS VCO.

S.Mohanty, D.Ghai, E.Kougianos, University of North Texas
B6.2: A Hardware Scheduler for Real Time Multiprocessor System on Chip.

N.Gupta, S.Mandal, J.Malave, A.Mandal, R.Mahapatra, Texas A & M University
C6.2: A Non Quasi-Static Small Signal Model for Long Channel Symmetric DG MOSFET

Sudipta Sarkar, IISc Bangalore,
A. Roy, Intel,
S. Mahapatra, IISc Bangalore
Industry Forum Details
15:45 16:10 A6.3: Optical Lithography Simulation with focus Variation Using Wavelet Transform.

R.Rodrigues, S.Kundu, University of Massachusetts, Amherst
B6.3: Safe-ERfair - A priori Overload Handling in Fair Scheduled Embedded Systems.

A.Sarkar, R.Nanda, S.Ghose, P.Chakrabarti, IIT Kharagpur
C6.3: A Novel Circuit to Optimize CLK-WL Path and Decoding Schemes in Memories

S. Jain, K. Srivastva, S. Kainth, Virage Logic
Industry Forum Details
16:10 16:30 Break
16:30 18:00 Theme Session: Affordable Technologies for Emerging Markets
Chair: Srivaths Ravi, Texas Instruments
16:30 17:00 "The Role OF VLSI for SATCOM Applications"
K. S. Dasgupta (ISRO)
17:00 17:30 "From Accessible Technologies to Affordable Solutions"
Sham Banerji (i2i TeleSolutions)
17:30 18:00 "Designing Technologies for the Rural Context"
William Thies (Microsoft Research India)
18:00 18:30 Break
18:30 18:45 Banquet Session
Chair: Srimat Chakradhar, NEC

Awards Distribution
18:45 19:30 Banquet Speech

Ahmad Bahai, (National Semiconductor)
19:30 20:30 Dinner
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