| Day 1 - Tuesday, January 5th, 2010 |
| 07:30 |
08:45 |
CONFERENCE REGISTRATION |
| 08:45 |
09:30 |
Conference Inauguration by Dr. Biswadip Mitra,
President, VSI and Managing Director, Texas Instruments India
- Address by General Chairs and Program Chairs. |
| 09:30 |
10:15 |
Chair: Niraj K. Jha, Princeton University |
| 10:15 |
11:00 |
Chair: Niraj K. Jha, Princeton University |
| 11:00 |
11:30 |
Break |
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Track A |
Track B |
Track C |
Ind. Forum |
| 11:30 |
12:45 |
SessionA1: Clocking and Physical Design
Chair: Bharadwaj Amrutur, IISc Bangalore |
Session B1: Application - specific Architectures
Chair: Debdeep Mukhopadhyay,
IIT Kharagpur. |
Session C1:
High-speed Links
Chair: Pradip Thaker, Analog Devices. |
|
| 11:30 |
11:55 |
A1.1: Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array.
V.Honkote, B.Taskin, Drexel University |
B1.1: Instruction Selection in ASIP Synthesis Using Functional Matching.
N.Arora, One97 Communications,
A.Kumar, IIT Delhi,K.Chandramohan, Synfora;
N. Pothineni, Google |
C1.1: Channel Optimization for the Design of High Speed I/O links.
R. Mandrekar,
Y. Zhou, S. Chun,
A. Haridass, J. Choi, N. Na, D. Dreps,
R. Weekly, P. Harvey, IBM |
|
| 11:55 |
12:20 |
A1.2: An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.
S. Saini, A. M. Kumar,
S. Veeramachaneni, IIIT Hyderabad;
M.B. Srinivas, BITS Hyderabad |
B1.2: A 90mW / GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-point and Integer Operands in 65nm.
S.Jain, V.Erraguntla, S.Vangal, Y.Hoskote, N.Borkar, T.Mandepudi, Karthik V.P., Intel |
C1.2: High Speed Serial Link Transmitter for 10Gig Ethernet Applications.
V.Muniyappa, N.Ramamoorthy, J.Reddy, IBM |
|
| 12:20 |
12:45 |
A1.3: A Graph-based I/O Pad Pre-placement Technique for Use with Analytic FPGA Placement Methods.
G.Grewal, M.Xu, University of Guelph, Ontario |
B1.3: A Reconfigurable Architecture for Secure Multimedia Delivery.
A.Pande, J.Zambreno, Iowa State University, Ames |
C1.3: Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O Link.
L. Raghavan, T. Wu, Rambus |
|
| 12:45 |
13:45 |
Lunch |
| 13:45 |
14:30 |
Chair: C. P. Ravikumar, Texas Instruments |
| 14:35 |
15:50 |
Session A2:
Analog / RF CAD
Chair: Jaggy Rao, Texas Instruments. |
Session B2: Efficient System Modeling and Design
Chair: Kanishka Lahiri, AMD. |
Session C2:
Circuit Design and Modeling I
Chair: Kota Murali, IBM |
|
| 14:35 |
15:00 |
A2.1: An Improvised MOS Transistor Model Suitable for Geometric Program based Analog Circuit Sizing in Sub-micron Technology.
S.DasGupta, P.Mandal, IIT Kharagpur |
B2.1: Bottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory Systems.
G.Hazari, M.Desai, G.Srinivas, IIT Mumbai |
C2.1: On Electrical Modeling of Imperfect Diffusion.
T.B.Chan, P.Gupta, University of California, Los Angeles |
|
| 15:00 |
15:25 |
A2.2: Towards Active-Passive Co-Synthesis of Multi-GigaHertz Radio Frequency Circuits.
R.Chakraborty, A.Sathanur, V.Jandhyala, University of Washington, Seattle |
B2.2: Implementation of a Novel Phoneme Recognition System using TMS320C6713 DSP
J. Manikandan,
B. Venkataramani, M.Bhaskar, K. Ashish,
R. Raghul, V.Mathangi,
NIT Trichy |
C2.2: An L-band Fractional-N Synthesizer with Noise-less Active Capacitor Scaling.
D.Sahu, S.Ganeshan, A.Lachhwani, R.Sachdev, Chandrashekar B.G, Texas Instruments |
|
| 15:25 |
15:50 |
A2.3: An Efficient Method for Bottom-Up Extraction of Analog Behavioral Model Parameters.
S.Pam, A.Bhattacharya, S.Mukhopadhyay, IIT Kharagpur |
B2.3: Design of Low-Cost High-performance Floating-point Fused Multiply-Add with Reduced Power.
Z.Qi, Q.Guo, X.Li, G.Zhang, W.Hu. Chinese Academy of Sciences |
C2.3: On-Chip Inductor-less DC-DC Boost Converter with Non-Overlapped Rotational-Interleaving Scheme.
T.Das, P.Mandal., IIT Kharagpur |
|
| 15:50 |
16:10 |
Break |
| 16:10 |
16:55 |
Session A3: Tackling Process Variations
Chair: TBD |
Session B3: Robust Design
Chair: M.Balakrishnan, IIT Delhi |
Session C3: Chip 2020
Chair: Susmita Sur-Kolay, ISI Kolkata.
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| 17:00 |
18:00 |
Executive/CTO Panel:
Moderator: Raman Santhanakrishnan (LSI Logic)
Panelists: Guru Ganesan, ARM, Vikas Kohli, Cadence, Santosh Kumar, Texas Instruments
Prof. Rahul De, IIM Bangalore, TBD, Xilinx, Ulf Schneider, Lantiq India |
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