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Conference Program

Schedule

Day 1 - Tuesday, January 4^th, 2011

07:30	08:45	CONFERENCE REGISTRATION
08:45	09:30	Inauguration
09:30	10:20	Keynote: Closing the Terahertz Gap Thomas H. Lee (Stanford University)
10:20	11:10	Keynote: Leading Minds to Billions : The Embedded Way Praveen Vishakantaiah (Intel)
11:10	11:30	Break

		Track A	Track B	Track C	Ind. Forum
11:30	12:45	Session A1: Serial Links Chair: Prakash Easwaran	Session B1: Simulation/Emulation of embedded systems Chair: Anshul Kumar	Session C1: Digital and Analog Test Generation Chair: C P Ravikumar	Session IFS1: Developing Embedded Solutions for the Emerging Market
		A1.1: 4×2Gbps Source-Synchronous Transmitter in 45nm CMOS Anant Kamath, Vikas Sinha and Sujoy Chakravarty Texas Instruments India Pvt. Ltd.	B1.1: Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction Su Myat Min, Jorgen Peddersen and Sri Parameswaran University of New South Wales	C1.1: Hazard-aware Directed Transition Fault ATPG for Effective Critical Path Test V. R. Devanathan and Ishaan Santhosh Shah Texas Instruments India and BITS Pilani	IFS1.1: Praveen Ganapthy Texas Instruments
		A1.2: Self-calibrating Equalizer for optimal jitter performance using on-chip eye monitoring Srinivasaraman Chandrasekaran, Kunal Desai, Arul Sendhil and William Ng Rambus	B1.2: AcENoCs: A Configurable HW/SW Platform for FPGA Accelerated NoC Emulation Swapnil Lotlikar, Vinayak Pai and Paul Gratz Texas A&M University	C1.2: Fault Collapsing Using A Novel Extensibility Relation Maheshwar Chandrasekar and Michael S. Hsiao Virginia Tech	IFS1.2: Design and Verification Challenges of Next Generation Embedded Solutions Pidugu Narayana Cypress
		A1.3: A New Double Data Rate (DDR) Dual-Mode Duobinary Transmitter Architecture Mrigank Sharad, Vijaya Sankara Rao P and Pradip Mandal IIT, Kharagpur	B1.3: A Library Development Framework for a Coarse Grain Reconfigurable Architecture Omer Malik, Ahmed Hemani and Muhammad Ali Shami Royal Institute of Technology (KTH), Sweden	C1.3: Optimized Multitone Test Stimulus Driven Diagnosis of RF Transceivers Using Model Parameter Estimation Aritra Banerjee, Vishwanath Natarajan, Shreyas Sen, Abhijit Chatterjee, Ganesh Srinivasan and Soumendu Bhattacharya Georgia Institute of Technology and Texas Instruments	IFS1.3: Embedded Solutions - Enhancing Listening Experience in Future Home Theatres Rajesh Mahapatra Analog Devices IFS1.4: Using ARM Physical Library to get GHz Performance on ARM Cores Jayantha Lahiri ARM
12:45	13:45	Lunch
13:45	14:30	Keynote: Bioelectronics Rahul Sarpeshkar (MIT)
14:30	14:40	Break
14:40	15:55	Session A2: Tolerant Design Chair: Vinod Menezes	Session B2: Embedded Tutorial 1 Chair:	Session C2: Power Gating and Sub-Threshold Design Chair: Nagi Naganathan	Session IFS2: Beyond Conventional EDA: What's on the horizon for CAD/EDA industry?
		A2.1: An Approach to Tolerate Process Related Variations in Memristor-Based Applications Jeyavijayan Rajendran, Harika Manem, Ramesh Karri and Garrett Rose Polytechnic Institute of New York University	B2.1: Heterogeneous Parallel Computing: From Chips to Clusters Srimat Chakradhar NEC Labs	C2.1: A Robust and Reconfigurable Multi-Mode Power Gating Architecture Z. Zhang, X. Kavousianos, K. Chakrabarty and Y. Tsiatouhas Duke University and University of Ioannina	IFS2.1: Avatars for the Maha-SoC Yuga Alok Mehrotra Magma
		A2.2: A SoI EEPROM Based Configuration Cell with Simple Scrubbing Detection Kashfia Haque and Paul Beckett RMIT University	B2.2: Adaptive high-speed serial link sub-systems for backplane communication Niranjan Talwalkar Teranetics	C2.2: MEMS-Based Power Gating for Highly Scalable Periodic and Event-Driven Processing M. B. Henry, R. Lylerly, A. Fruehling, D. Peroulis and L. Nazhandali Virginia Tech and Purdue University	IFS2.2: Model Driven Development - The Right Approach for System Level Design Mallikarjun Bande Mentor Graphics
		A2.3: Power Scalable Digital Baseband Architecture for IEEE 802.15.4 Satyam Dwivedi, Bharadwaj amrutur and Navakanta Bhat IISc, Bangalore		C2.3: True Minimum Energy Design Using Dual Below-Threshold Supply Voltages Kyungseok Kim and Vishwani Agrawal Auburn University	IFS2.3: EDA 360 - The Way Forward Saugat Sen Cadence IFS2.4: Fast Path from Algorithm to Silicon! Tanaji Hanchate T Synopsis Partner Dgipro
15:55	16:15	Tea
16:15	17:30	Session A3: Oscillators and PLLs Chair: Vasantha Erraguntla	Session B3: New Directions for Emerging Applications of Layout and Routing Chair: Sampath Dechu	Session C3: Variation aware design Chair: Susmita Sur-Kolay	Industry Forum
		A3.1: Evolution of Oscillation in a Quadrature Oscillator Diptendu Ghosh and Ranjit Gharpurey The University of Texas at Austin	B3.1: A GPU Floorplanning Algorithm: Specification, Analysis and Optimization Yiding Han, Koushik Chakraborty, Sanghamitra Roy and Vilasita Kuntamukkala Utah State University	C3.1: LA-LRU: A Latency-Aware Replacement Policy for Variation Tolerant Caches A. Jain, A. Shrivastava and C. Chakrabarti Cambridge Silicon Radio and Arizona State University	Panel IFP1: VLSI and Embedded Design in India - Products or Services? Where can we add most value? Panelists: B Sridhar (CMC) Mohan Narasimhan (CYPRESS) Raman Santhanakrishna (LSI LOGIC) Praveen Ganapathy (TEXAS INSTRUMENTS) Sreedhar D N (TCS)
		A3.2: Quadrature Error Compensation for Jitter Reduction in High Speed Clock and Data Recovery Circuits Kunal Desai and Vijay Krishna Rambus India Design Center	B3.2: Automated physical design of microchip based capillary electrophoresis systems Yih-Ling Hsieh and Tsung-Yi Ho National Cheng Kung University, Taiwan	C3.2: Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization S. Banerjee, J. Mathew, D. K. Pradhan, S. P. Mohanty and M. Ciesielski University of Bristol, University of North Texas, and University of Massachusetts	IFST: Towards Newer Paradigms of Research and Innovation - An Overview of IIT Madras Research Park Sandhya Sekhar IIT Madras Research Park
		A3.3: A 1.8GHz Digital PLL in 65nm CMOS Biman Chattopadhyay, Anant Kamath and Gopalkrishna Nayak Texas Instruments India Pvt. Ltd.	B3.3: Layout aware solution preparation for Bio chemical analysis on a digital microfluidic biochip S. Roy, B. B. Bhattacharya, P. P. Chakrabarti and K. Chakrabarty IIT Kharagpur, ISI Kolkata and Duke University	C3.3: VaROT: Methodology for Variation-Tolerant DSP Hardware Design Using Post-Silicon Truncation of Operand Width K. Kunaparaju, S. Narasimhan and S. Bhunia Case Western Reserve University
17:30	18:00	Break
18:00	20:00	Cultural program

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