Abstract:Conventional wisdom states that the more experience a semiconductor designer has, the better. Years of direct, hands-on work gives designers unique insights into anticipating and solving problems. But there is a hidden downside to experience: it can harden into habit and breed resistance to change. This quiet but potent liability is becoming a pressing concern as the industry faces a host of challenges in next-generation semiconductor design, from low power design to improving yields through design for manufacturing.

That is why India’s future looks so promising in semiconductor design. A growing force of fresh well-educated designers, working in partnership with established multi-national companies, positions India at the forefront of assimilating new design methodologies. Dr. Rhines’ will examine three areas—semiconductor place & route, low power design and verification—that are undergoing major transformations, offering India its greatest potential to move to the vanguard of design. In each of these cases, old methodologies will certainly be replaced in the next few years and the first to adopt will be the first to gain significant competitive advantage.

Abstract: High-Performance Throughput Computing, achieved through designed-from-scratch processors composed of multiple multithreaded cores, offers an unprecedented opportunity to create a new generation of pipelines that deliver both high throughput performance and high single-thread performance. A checkpoint-based architecture that offers a new execution model, perhaps the only novel one in over a decade, forms the cornerstone of the Rock microprocessor. Hardware threads are spawned and they speculatively execute and retire instructions out-of-order. Power efficiency is emphasized by maximizing the utilization of pipeline stages, through temporal threading, and functional units, through spatial threading and speculation. This pipeline is embedded multiple times in our future high-end 65nm and 45nm processors that form the cornerstone a broad line of systems ranging from small servers to supercomputers. As important as the Throughput Computing paradigm, is the enablement of parallel software. Rock should be the first processor to support Transactional Memory, a leading candidate to deliver high-performance scalable parallel applications through composable software.

Marc Tremblay is currently CTO for Sun's Microelectronics business unit where he sets the direction for Sun's processor roadmap and related technology. His mission is to move Sun's entire product line to the Throughput Computing paradigm, incorporating techniques he has helped develop--including chip multiprocessing, chip multithreading, speculative multithreading, assist threading and transactional memory. Tremblay's latest endeavor is Sun's Project ROCK, a third generation chip multithreading processor due out in 2008. He has worked on multithreaded and multicore processors for more than 12 years.

Prior to becoming CTO, he was co-architect for Sun's UltraSPARC I, the MDR Microprocessor of the Year in 1995, and chief architect for the UltraSPARC II microprocessor. He was chief architect for Sun's MAJC program, which was nominated for best emerging technology in 1999 and best media processor in 2000 by MDR Analysts. Tremblay also architected the picoJava processor core, a Java bytecode engine, whose components can be found in mobile phones and smart cards worldwide.

Tremblay holds a master's degree and doctorate in computer science from UCLA and a bachelor's in physics engineering from Laval University in Canada. He holds more than 120 U.S. patents in various aspects of computer architecture. Tremblay was nominated for Innovator of the Year by EDN Magazine in 1999. He was co-chair of the Hot Chips 2000 conference, delivered the keynote address for the 31st Annual International Symposium on Computer Architecture (ISCA 2004) in Munich, Germany, and recently delivered the keynote address at the International Computer Symposium (ICS) 2006 in Australia. Tremblay taught a graduate course on computer architecture at Stanford in 2002. He is a member of IEEE and ACM.

Abstract: There are a number of trends sweeping through the telecommunications space that will ultimately have a dramatic impact on the Semiconductor industry. The primary trend is that the world will be more “wire-less” specifically in the access space. The advent of 4G wireless technologies, specifically WiMAX and Long Term Evolution (LTE), will allow wireless carriers to offer services that can almost rival conventional broadband wireline services based on XDSL and cable. As end users transition to high speed wireless services, the network architecture will become more distributed, causing the intelligence of the network to migrate to the handset, femtocell, home gateway, and the base station. These elements of the network will need to be highly programmable and specialized. The cost of home gateway and handset will rise to approximately 60% or more of the total cost, while base station and other access system, along with the core network would constitute the other 40%.
This trend will drive the semiconductor industry to focus more on low power design while seeking to improve performance. Because of potential for high volume in handset, femtocells and homegateway, low power process will receive more emphasis from foundries. Further, the reduction of size required in these devices will require innovation in packaging and thermal management. The system vendors would also demand the opportunity for adding differentiation and that will require the implementation to be highly programmable in handset, femtocell and home gateway.
This presentation will, in short, explore a future world “Without Wire” and its impact on the semiconductor industry as we know it today.

Dr. Santanu Das is a founder of TranSwitch Corporation in Shelton, CT, which started operation in 1989, and is the President and CEO of the company. Prior to TranSwitch Corporation, he held various positions, including President of Spectrum Digital Corporation, a telecommunications equipment company, where he worked from 1986 through August of 1988. Before joining Spectrum, he held various executive positions, including Director, Applied Technology Division of ITT Corporation’s Advanced Technology Center in Shelton, CT. He received his B.E. and M.E. degrees in Electronics and Telecommunications Engineering from Jadavpur University, Calcutta, India, in 1965 and 1968, respectively, and his Doctor of Science (D.Sc) in Electrical Engineering from Washington University, St. Louis, U.S.A., in 1973. Dr. Das is a member of the Institute of Electrical and Electronics Engineers (IEEE), and ACM., U.S.A. He has authored and/or co-authored more than 25 papers in different journals, magazines, and conference proceedings. He is a frequent speaker at industry forums and has been invited to speak at major technical and non-technical functions and conferences. Dr. Das has been granted a number of patents in his field. Dr. Das received the "Alumni Achievement Award"

Abstract: Researchers in emerging models and technologies seek to advance the frontiers of computer and information sciences and engineering by combining the knowledge and technical advancements in disparate areas of research such as biological systems, quantum information processing, and nanoscale science and engineering. In order to bring about fundamental changes in software, hardware and architectures of the future-generation computing and communication systems, interdisciplinary collaborations among computer scientists, engineers in various fields, physicists, chemists, mathematicians, and biologists are imperative. This talk will outline the directions of research activities in nanoelectronics after briefly alluding to some research projects that are currently being funded by the Emerging Models and Technologies (EMT) program of the National Science Foundation. The EMT program primarily incubates innovative research ideas that are likely to bring about radical and path-breaking changes in nanoelectronics, quantum computing, biologically inspired computing, computational biology, and biological computing. This synergistic research is expected to spur the growth of a combined biotech, nanotech and infotech market well over one trillion US dollars in or about 2015, a target set by a National Nanotechnology Initiative (NNI) study group for the nanotech market for materials, chemicals, electronics, photonics, and pharmaceuticals alone.

Abstract: This talk covers design considerations and solutions for energy-constrained microsystems such as sensor networks, multimedia devices, RFID systems and portable medical electronics. Energy scavenging techniques such as vibration-to-electric conversion and wireless power transmission will be presented. A system-level approach is required to minimize the overall energy dissipation. A major opportunity to reduce the power dissipation of digital circuits is to scale the power supply voltage below the device thresholds (i.e., sub-threshold operation). The opportunities and challenges associated with sub-threshold design will be presented. This includes variation-aware design for logic and SRAM circuits, efficient DC-DC converters for ultra-low-voltage delivery, and algorithm structuring to support extreme parallelism. Energy in analog baseband processing can be reduced through low-voltage design, parallelism and the use of circuits that compensate for device variations. The use of highly digital architectures for wireless communication circuits can also significantly reduce system energy dissipation.

Biography: Anantha P. Chandrakasan received the B.S, M.S. and Ph.D. degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley, in 1989, 1990, and 1994 respectively. Since September 1994, he has been with the Massachusetts Institute of Technology, Cambridge, where he is currently the Joseph F. and Nancy P. Keithley Professor of Electrical Engineering.
He was a co-recipient of several awards including the 1993 IEEE Communications Society's Best Tutorial Paper Award, the IEEE Electron Devices Society's 1997 Paul Rappaport Award for the Best Paper in an EDS publication during 1997, the1999 DAC Student Design Contest Award, the first place in the 2004 DAC/ISSCC Student Design Contest Award (operational category), and the ISSCC 2007 Beatrice Winner Award for Editorial Excellence. He held the Analog Devices Career Development Chair from 1994 to 1997. He received the NSF Career Development award in 1995, the IBM Faculty Development award in 1995 and the National Semiconductor Faculty Development award in 1996 and 1997.

Abstract: This plenary talk will outline the evolution of supercomputers in terms of both architectures and enbaling technology (hardware and software). The state-of-the-art will be reviewed. In perspective will be discussed the distinguishing features of the Eka Supercomputer developed in Pune by Computational Research Laboratories. The process of developing Eka --- which, with a sustained rating of 120 TF, is the fourth fastest in the world and the fastest in Asia --- will be presented. The talk will then cover applications of supercomputers, the challenges faced in scaling up of these applications and the possible ways to meet these challenges.

Speaker: Sunil Sherlekar is the Head of Embedded Systems Innovation Lab. at Tata Consultancy Services (TCS) and a member of the TCS Corporate Technology Board. He is also one of the founders of Computational Research Labs. Ltd. (CRL), a subsidiary of Tata Sons Ltd. CRL aims to establish itself in a leadership position in High-Performance Computing globally. Before assuming these positions, he was the founding CTO of Sasken Communication Technologies for 10 years. He was on the faculty of Computer Sc. & Engg. at IIT Bombay from 1982 to 1992 where he was engaged in research in EDA and architectures for signal processing. He has a B. Tech. (EE), M. Tech. (Computer Sc. & Engg) and Ph. D. all from IIT Bombay. He has published several papers in journals and conferences in the areas of EDA and signal processing architectures and a book on VLSI Architectures for signal processing. He has been the program chair and general chair of several international conferences and is on the steering committee of the Asia & South Pacific Design Automation Conference (ASPDAC). He is also an Adjunct Professor at IIT Bombay. In this role, he leads the TCS-sponsored VLSI Lab. This lab. supports M. Tech., Dual-degree and Ph. D. students through equipment, scholarships and technical interaction.

Speaker: N. Seetha Rama Krishna, with two decades of Super Computing Experience, headed the EKA supercomputing system team at Computational Research Laboratories. Before this he was involved in all PARAM super computing projects of CDAC (Centre for Development of Advanced Computing) as the Chief Architect. He was instrumental in establishing NSF (National Supercomputing Facility) in Pune and CTSF (CDAC TeraScale Supercomputing Facility) in Bangalore. He also initiated and led the execution of the GRID GARUDA project. Krishna has been a part of several international deals for setting up HPC facilities at Russia, Singapore, Ghana, Germany and Canada. He has been the chief consultant to many large public sector companies and govt. organizations & scientific labs in India. Krishna's main technical interests are Enterprise HPC, Grid computing and Application Specific Supercomputing. He has won several PARAM Awards for his contributions to the supercomputing efforts of CDAC and has been the preferred speaker in supercomputing, grid computing and storage fields. He is an electronics and communication engineering graduate from Osmania University with a Post-Graduate Management diploma in Business Development.

Abstract: Advancement in technology has lead to the fabrication of electronic systems at the molecular level. It is clear that the right computational support will substantially reduce the development time to develop a broad-based molecular manufacturing capability. Computer-aided design systems for nanoscale electronics are needed to enable the design of complex systems. A methodology for nanoelectronics that is analogous to the VLSI design methodology of physical, structural and behavioural models needs to be developed. Some of the abstractions such as system, register and logic of VLSI design can be used with some modification for nanoelectronics. However, circuit, device and material levels will have to be different and are not available today. It is expected that, unlike VLSI design, there will not be a clean separation between the designer and the fabrication process for nanoelectronic systems. In the nanoscale design flow, process and device simulators will be centre-stage because of self assembly characteristics. The talk will outline the challenges and indicate how supercomputers can help meet them.

Speaker: Rajendra Patrikar is a Member of Techical staff at Computational Research Laboratories (CRL). Before joining CRL he was a Professor of Electronics and Computer Science at Vishweshwaraiya National Institute of Technology, Nagpur. He has an M.Tech in Electrical Engineering and a Ph.D. from IIT Bombay where he was a Research engineer in the Microelectronics Project. He was on the faculty of IIT Bombay after working for a year at Computervision R&D Pune. Then he moved to Singapore to work at TECH Semiconductor in their Advanced Device Technology Department for three years. He then moved to the Institute of High Performance Computing Singapore where he carried out research work in the area of CAD for VLSI and nanoelectronics. He has published about 45 papers in international journals, conferences and has filed for one patent in USA in the area of VLSI testing.