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Conference
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The 21st International Conference on VLSI Design
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The 7th International Conference on Embedded Systems
| Hyderabad International Convention Centre, Hyderabad, January 4-8, 2008 |
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| Tentative Technical Program (Version as of December 23, 2007) |
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Maintaining the tradition of the conference, the three-day technical program of the joint conference on January 6-8, 2008 will feature keynote and plenary talks from world leaders, high-quality technical paper presentations that reflect the state-of-the-art in VLSI Design and Embedded Systems. It also includes embedded tutorials, a panel discussion, and a parallel track for industry forum. Registration information for the conference is available at . The conference schedule is available at . |
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| Presentation time for contributed Papers : |
20 mins |
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| Tutorial Program |
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World-renowned experts will offer eight high-quality, full-day tutorials as part of the conference on January 4 & 5, 2008. All tutorials will run from 9:00 AM to 5:00 PM, with a 1-hour lunch break at 12.30 pm and two 30-minute tea breaks at 10:30 am and 3:00 pm. One must register for tutorials separately. Tutorial Registration information is available at . |
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Tutorials: January 4, 2008 (Friday) |
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Gateway to Chips : High Speed I/O Signalling
and Interface
Nidhir Kumar, ARM Embedded Technologies.
Senthil N. Velu, ARM Embedded Technologies .
Rajan Verma, ARM Embedded Technologies. |
DFM / DFT / SiliconDebug / Diagnosis
Nagesh Tamarapalli, AMD India Design Center.
Srikanth Venkataraman, Intel Corporation.
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Oversampling Analog-to-Digital Converter Design
Shanthi Pavan, IIT, Madras.
Nagendra Krishnapura , IIT, Madras. |
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Programming and Performance Modelling of Automotive ECU Networks (Half Day)
Samarjit Chakraborty , National University of Singapore
S. Ramesh, General Motors R&D, India Science Laboratory, Bangalore
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Architecture Exploration for
Low Power Design (Half Day)
Vinod Kathail, Synfora, Inc.
Tom Miller, Sequence Design, Inc.
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Tutorials: January 5, 2008 (Saturday) |
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Memory Design and Advanced Semiconductor Technology (Full Day)
- D. Harame, S.S. Iyer, J.S. Watts, R. Joshi, and J.E. Barth Jr., IBM
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Scan Delay Testing of Nanometer SoCs
Adit D. Singh, Auburn University |
| Cross-Layer Approaches to Designing Reliable Systems using Unreliable Chips
Fadi Kurdahi, UCI
Nikil Dutt, UCI
Ahmed Eltawil, UCI
Sani Nassif, IBM
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OpenSPARC - A scalable Chip Multi-Threading Design (Half Day)
Dwayne Lee, Sun Microsystems, Inc.
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Implementing the Best Processor Cores (Half Day)
Vamsi Boppana, Technology Open-Silicon, Inc., CA
Rahoul Varma, Manager, ARM Embedded Technologies, Bangalore
S. Balajee, Texas Instruments India, Bangalore
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Saturday, January 5, 2008 |
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| Inaugural Ceremony |
Keynote Presentation
Dirk Meyer, President and COO, AMD
Chair: Srimat Chakradhar |
| Dinner |
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Sunday, January 6, 2008 |
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Plenary
Chair:
Plenary Keynote Address I
Disruptive Methodologies, India’s Opportunity
Walden C. Rhines, CEO, Mentor Graphics
Plenary Keynote Address II
System design challenges and solutions for future nanoscale process technologies
Alain Artieri, Senior System Architect, STMicroelectronics, France
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| Morning Tea / Coffee |
| Inauguration of Technical Exhibition |
SESSION A1
Fault Tolerance
Session chair:
Mike Bushnell |
SESSION B1
Wireless/Communication
Session chair:
Nitin Chandrachoodan |
SESSION C1
Embedded Systems
Session Chair:
Preeti Panda |
SESSION D1
Technology
Session Chair:
NS Nagaraj |
SESSION E1
Industry Forum I |
A Power Efficient Approach to Fault-Tolerant Register File Design
Mojtaba Amiri-Kamalabad,
Seyed Ghasem Miremadi,
Mahdi Fazeli
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Retimed Decomposed Serial Berlekamp-Massey (BM) Architecture for High-Speed Reed-Solomon Decoding
Shahid Rizwan
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Multimedia Tools and Architectures for Hardware/Software Co-Simulation of Reconfigurable Systems
Valery Sklyarov,
Iouliia Skliarova,
Bruno Pimentel, Manuel Almeida
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Compact Modeling of Suspended Gate FET
Y. S. Chauhan,
D. Tsamados,
N. Abelé,
C. Eggimann,
M. Declercq,
A. M. Ionescu
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Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS
Maryam Ashouei,
Adit D. Singh,
Abhijit Chatterjee |
Exploring the Processor and ISA Design for Wireless Sensor Network Applications
Shashidhar Mysore,
Banit Agrawal,
Frederic T. Chong, Timothy Sherwood
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A Modeling of a Dynamically Reconfigurable Processor using SystemC
Junji Kitamichi,
Koji Ueda,
Kenichi Kuroda |
Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies
Aditya Bansal,
Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy |
Single Error Correcting Finite Field Multipliers over GF(2m)
J. Mathew, A Costas,
H. Mohammad,
A Jabir,
D.K Pradhan |
Concurrent Multi-Dimensional Adaptation for Low-Power Operation in Wireless Dev
Rajarajan Senguttuvan, Shreyas Sen,
Abhijit Chatterjee |
A Scalable and Reconfigurable Coprocessor for Image Composition
Jalaj Jain
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Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design
Amith Singhee, Jiajing Wang, Benton H. Calhoun,
Rob A. Rutenbar |
A Robust Architecture for Flip-Flops Tolerant to Soft Errors and Transients from Combinational Circuits
Aditya Jagirdar,
Roystein Oliveira,
Tapan J.Chakraborty
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Adaptive Signal Scaling Driven Critical Path Modulation for Low Power Baseband OFDM Processors
Muhammad M. Nisar, Rajarajan Senguttuvan, Abhijit Chatterjee
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Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
Alexandru Andrei,
Petru Eles, Zebo Peng, Jakob Rosen
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NBTI Degradation: A Problem or a Scare?
Kewal K. Saluja, Shriram Vijayakumar, Warin Sootkaneung, Xaingning Yang |
Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation Bypass
Kaushal R. Gandhi, Nihar R. Mahapatra
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Fault Tolerant Dynamic Antenna Array In Smart Antenna System Using Evolved Virtual Reconfigurable Circuit
D.Dhanasekaran, K.Boopathy Bagan |
An Approach to Software Performance Evaluation on Customized Embedded Processors
Soumyajit Dey,
Monu Kedia,
Anupam Basu |
On-Chip Process Variation Detection using Slew-Rate Monitoring Circuit in Sub-100nm CMOS Technology
Amlan Ghosh, Rahul M. Rao,
Jae-joon Kim, Richard B. Brown, Ching-Te Chuang |
| Lunch |
SESSION A2
Testing/DFT
Session Chair:
Adit Singh |
SESSION B2
Interconnects
Session Chair:
Harindranath Parameswaran |
SESSION C2
Architecture
Session Chair:
Vijay Degalahal |
SESSION D2
Analog
Session Chair :
Vinita Vasudevan |
SESSION E2 Industry Forum II |
On Common-Mode Skewed-Load and Broadside Tests
Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu |
Wiring-Area Efficient Simultaneous Bidirectional Point-to-Point Link for Inter-Block On-Chip Signaling
Charbel J. Akl,
Magdy A. Bayoumi |
Dynamic Aggregation of Virtual Addresses in TLB using TCAM Cells
Rupak Samanta, Jason Surprise,
Rabi. N. Mahapatra
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Mismatch Aware Analog Performance Macromodeling using Spline Center and Range Regression on Adaptive Samples
Shubhankar Basu, Balaji Komminneni, Ranga Vemuri
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Testing Flash Memories for Tunnel Oxide Defects
Mohammad Gh. Mohammad,
Kewal K. Saluja
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Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor
Andy Lambrechts, Praveen Raghavan,
Murali Jayapala,
Francky Catthoor,
Diederik Verkest
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Continuous Frequency Adjustment Technique Based on Dynamic Workload Prediction
Hwisung Jung, Massoud Pedram
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An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators
J. Ramirez-Angulo,
Lalitha M. Kalyani-Garimella, Annajirao Garimella,
Sri Raga Sudha Garimella,
A. Lopez-Martin,
R.G. Carvajal |
On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set
Hafizur Rahaman,
Dipak K. Kole,
Debesh K.
Das,
Bhargab B. Bhattacharya |
Integrated TIA-Equalizer for High Speed Optical Link
Saurav Bandyopadhyay, Pradip Mandal,
Stephen E. Ralph, Kenneth Pedrotti |
Recursive versus Iterative Algorithms for Solving Combinatorial Search Problems in Hardware
Iouliia Skliarova,
Valery Sklyarov,
Bruno Pimentel |
Highly Linear Wide Dynamic Range CMOS Transconductance Multiplier using Source-degeneration V-I Converters
Sri Raga Sudha Garimella |
Memory Yield Improvement through Multiple Test Sequences and Application aware Fault Models
Aman Kokrady,
C.P. Ravikumar,
Nitin Chandrachoodan |
Single Edge Clock (SEC) Distribution for Improved Latency, Skew, and Jitter
Jeff Mueller,
Resve Saleh |
Exhaustive Enumeration of Custom Instructions for Extensible Processors
Nagaraju Pothineni
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Chaos-modulated ramp IC for EMI reduction in PWM buck converters- design and analysis of critical issues
Rupam Mukherjee, Amit Patra, Soumitro Banerjee |
Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths
Irith Pomeranz, Sudhakar M. Reddy
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Threshold Voltage Control through Multiple Supply Voltages for Power-efficient FinFET Interconnects
Anish Muttreja,
Prateek Mishra,
Niraj K. Jha
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An Optimal Multi-Functional Unit Dynamic Instruction Selection Logic at Submicron Technologies
Terrell Bennett,
Rama Sangireddy
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A Fast settling 100dB OPAMP in 180nm CMOS process with compensation based optimization
Amal Kumar Kundu, Subho Chatterjee,
Tarun Kanti Bhattacharyya |
Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity
Irith Pomeranz, Sudhakar M. Reddy
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Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation
Sampo Tuuna,
Ethiopia Nigussie,
Jouni Isoaho,
Hannu Tenhunen
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A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores
Rajaraman Ramanarayanan,
Sanu Mathew,
Vasantha Erraguntla, Shay Gueron,
Ram Krishnamurthy
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VLSI Implementation of a Digitally Tunable Gm-C Filter with Double CMOS Pair
S.Ramasamy, B.Venkataramani, K.Anbugeetha
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A partitioning based Physical Scan Chain Allocation Algorithm that minimizes Voltage Domain Crossings
Nilabha Dev, Sandeep Bhatia, Subhasish Mukherjee, Sue Genova, Vinayak Kadam
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Exploiting Variable Cycle Transmission for Energy-Efficient on-Chip Interconnect Design
T.V. Kalyan,
Madhu Mutyam,
P.V. Sankara Rao
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Dynamic Error Detection for Dependable Cache Coherency in Multicore Architecture
Hui Wang,
Sandeep Baldawa, Rama Sangireddy
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A 9 bit 400 MHz CMOS double-sampled Sample-and-Hold Amplifier
Sounak Roy,
Prof. Swapna Banerjee
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| Afternoon Tea |
Panel Discussion
Title: Memory requirements of next generation chips and systems
Organizer: A.P.K. Sreekumar, Rambus |
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Monday, January 7, 2008 |
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Plenary Session
Chair:
Plenary Keynote Address I
Design Considerations for Next Generation Micro-Power Systems
Anantha Chandrakasan, MIT
Plenary Keynote Address II
Partnerships for Success: DFM, DFT and the Value of Accelerated Yield Learning the IFM World
Michael Campbell, Senior Vice President of Engineering, Qualcomm
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| Morning Tea |
SESSION A3
Physical Design/CAD
Session chair:
Vidyasagar Ganesan |
SESSION B3
Low Power - I
Session chair:
Saraju Mohanthy |
SESSION C3
NoC/SoC
Session chair:
S. Srinivasan |
SESSION D3
Nano
Session chair:
Kewal Saluja |
SESSION E3
Industry Forum III |
A New Approach for Estimation of On-Resistance and Current Distribution in Power Array Layouts
Jyotirmoy Ghosh, Siddhartha Mukhopadhyay,
Amit Patra,
Barry Culpepper,
Tawen Mei
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Incorporating PVT Variations in System-level Power Exploration of On-Chip Communication Architectures
Sudeep Pasricha, Young-Hwan Park, Nikil Dutt,
Fadi J Kurdahi
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MoCSYS: A Multi-Clock Hybrid Two-Layer Router Architecture and Integrated Topology Synthesis Framework for System-Level Design of FPGA based On-Chip Networks
Arun Janarthanan,
Karen A. Tomko
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Single Event Upset: An Embedded Tutorial
Fan Wang,
Vishwani D. Agrawal
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An Elitist Non-Dominated Sorting based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning
Pradeep Fernando, Srinivas Katkoori
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Energy - Efficient, High Performance Circuits for Arithmetic Units
Sundeepkumar Agarwal,
Pavankumar V K, Yokesh R
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MPSoC Communication Architecture Exploration Using an Abstraction Refinement Method
Hao Shen,
Frédéric Pétrot
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Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture
Muzaffer O. Simsir, Srihari Cadambi,
Franjo Ivancic,
Martin Roetteler,
Niraj K. Jha
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Fast Congestion Aware Routing for Pin Assignment
Shashank Prasad |
Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters
Qingli Zhang,
Jinxiang Wang |
A Pseudo-exhaustive Test Strategy Based on Flooding for NoC Switches
Mahshid Sedghi, Elnaz Koopahi, Armin Alaghi, Mahmood Fathy, Zainalabedin Navabi |
Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits
Rajat Subhra Chakraborty,
Swarup Bhunia |
A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions
Nagaraju Pothineni, Anshul Kumar, Kolin Paul
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Robust Level-Shifter Design for Adaptive Voltage Scaling
Ankur Gupta,
Rajat Chauhan,
Vinod Menezes,
Vikas Narang,
Roopashree H.M
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High-Level Modeling Approach for Analyzing the Effects of Traffic Models on Power and Throughput in Mesh-based NoCs
Somayyeh Koohi, Mohammad Mirza-Aghatabar, Shaahin Hessabi, Masoud Pedram
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A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor
Biswajit Ray,
Santanu Mahapatra
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Addressing the Challenges of Synchronization/ Communication and Debugging Support in Hardware/Software Cosimulation
Banit Agrawal, Chulho Shin, Simon Yoon, Timothy Sherwood
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Low Power Hardware Architecture for VBSME Using Pixel Truncation
Asral Bahari,
Tughrul Arslan,
Ahmet T. Erdogan
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PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors
Deepa Kannan,
Aseem Gupta,
Aviral Shrivastava,
Fadi Kurdahi,
Nikil Dutt
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Design of Reversible Finite Field Arithmetic Circuits with Error detection
J. Mathew,
H. Rahman,
Bibita Roslid Jose,
D.K. Pradhan |
| Lunch |
SESSION A4
Verification
Session chair:
Bharadwaj Amrutur |
SESSION B4
Low Power - I
I
Session chair:
Srinivas Katkoori |
SESSION C4
Architecture/Arithmetic
Session chair:
Pradip Thaker |
SESSION D4
Design/MEMS/Optical
Session chair:
Bernard Courtois |
SSESSION E4
Industry Forum IV |
Circuit Reconvergence Static Learning for SAT Solvers
Yinlei Yu, Cameron Brien, Sharad Malik
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Energy Reduction in SRAM using Dynamic Voltage and Frequency Management
Mohammed I. Shareef, Pradeep Nair,
Amrutur Bharadwaj
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Stall Power Reduction in Pipelined Architecture Processors
Pejman Lotfi-Kamran,
Ali-Asghar Salehpour,
Amir-Mohammad Rahmani,
Ali Afzali-Kusha
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New Jitter Reduction Technique for High-Speed
Serializer-Deserializer (SERDES) and Phase-Locked Loop Circuits (Invited Paper)
Hari Venkatanarayanan,
Michael L. Bushnell |
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Efficient Linear Macromodeling via Discrete-Time Time-Domain Vector Fitting
Chi-Un Lei,
Ngai Wong
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Unified Vdd - Vth optimization based DVFM controller for a Logic block
N S Sreeram,
S A Kannan,
Bharadwaj S Amrutur
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A Novel Carry-look ahead approach to an Unified BCD and Binary Adder/Subtractor
Sreehari Veeramachaneni, Kirthi Krishna, M Prateek Gundannavar Vijay Bharat Sankhlecha Subroto Sen, M.B.Srinivas
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GyroCompiler: A Soft IP Model Synthesis and Analysis Framework for Design of MEMS Based Gyroscopes
Jairam Sukumar, Navakanta Bhat
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Formal verification of a public-domain DDR2 controller design
Abhishek Datta, Vigyan Singhal
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Temperature and Process Variations aware Power Gating of Functional Units
Aviral Shrivastava, Deepa Kannan, Sarvesh Bhardwaj, Sarma Vrudhula |
Memory Architecture Exploration Framework for Cache Based Embedded SoC
T.S. Rajesh Kumar,
C.P. Ravikumar, R.Govindarajan
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Behavioral modeling of a CMOS compatible high precision MEMS based electron tunneling accelerometer
T.K. Bhattacharya, Anandaroop Ghosh
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Enhanced TED: A New Data Structure for RTL Verification
Pejman Lotfi-Kamran,
Mehran Massoumi, Mohammad Mirzaei, Zainalabedin Navabi |
A Robust Top-down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits
Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri
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A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block using Symmetrized 9T SRAM Cell with Controlled Read
Satish Anand V,
Sivakumar Bondada, Bharadwaj S. Amrutur
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An optical reconfiguration system with four-contexts
Naoki Yamaguchi, Minoru Watanabe
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Simulation Acceleration with HW Re-compilation Avoidance
Kyuho Shim
, Maciej Ciesielski, Seiyang Yang
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Total Power Minimization in Glitch-Free CMOS Circuits
Yuanlin Lu,
Vishwani D. Agrawal
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A Novel Approach to Design BCD Adder and Carry Skip BCD Adder
Md. Mahmudul Hasan, Ashis Kumer Biswas, Ahsan Raja Chowdhury, Mosaddek Hasan, Hafiz Md. Hasan Babu
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An acceleration and optimization method for optical reconfigurations
Minoru Watanabe,
Naoki Yamaguchi
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A Module Checking based Converter Synthesis
Roopak Sinha, Partha S Roop, Samik Basu,
Zoran Salcic
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Power Reduction of Functional Units considering Temperature and Process Variations
Aviral Shrivastava, Deepa Kannan, Sarvesh Bhardwaj, Sarma Vrudhula
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A Merged Synthesis Technique for Fast Arithmetic Blocks involving Sum-of-Products and Shifters
Sabyasachi Das,
Sunil P. Khatri
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0.35µ, 1GHZ, CMOS Timing Generator Using Array Of Digital Delay Lock Loops
V.B Chandratre,
Menka Tewani,
S.Balaji
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| Afternoon Tea |
PANEL DISCUSSION
Title: New Frontiers in Energy Efficient Computing with Integrated Multi-Core Platforms in Nanoscale CMOS
Organizer/Moderator: Vivek De, Intel
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Banquet Speech
FPGA: The future platform for transforming, transporting and computing
Ivo Bolsens, VP and CTO, Xilinx , USA
Chair: |
| AWARDS |
| Banquet Dinner |
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Tuesday, January 8, 2008 |
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Tuesday Morning Plenary Session
Chair:
Plenary Talk 1:
Embedded Processor Design Challenges & Opportunities for Converging Multi-Media and Communications
Applications
Speaker: Dr. Ramesh Senthinathan, Senior Director of Engineering, Broadcom Corporation
Plenary Talk 2:
Trends in Telecommunication and Their Impact on VLSI
Speaker: Dr. Santanu Das, President and CEO, TranSwitch Corporation
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Plenary Keynote
Topic: TBA
Speaker: Marc Tremblay, CTO, SUN Microsystems |
| Morning Tea |
SESSION A5
Synthesis
Session chair:
Anshul Kumar |
SESSION B5
Low Power - III
Session chair:
Tarun Bhattacharyya |
SESSION C5
Security
Session chair
C.P. Ravikumar |
Organizer:
Nagi Naganathan
Session Chair: Gurudutt Bansal
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SESSION E5
Industry Forum V |
Variability-tolerant Register-transfer Level Synthesis
Anish Muttreja,
Srivaths Ravi,
Niraj K. Jha
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A Low Voltage, Low Ripple, on Chip, Dual Switch-Capacitor Based Hybrid DC-DC Converter
Kaushik Bhattacharyya, Pradip Mandal
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Single Chip Encryptor/Decryptor Core Implementation of AES Algorithm
Monjur Alam, Dipanwita Roychowdhury
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“Standards in EDA: An Introduction”,
Nagi Naganathan, LSI Corp. |
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A Galois Field Based Logic Synthesis Approach with Testability
J. Mathew,
H. Rahaman,
D. K. Pradhan
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Voltage and Temperature Scalable Standard Cell Leakage Models Based On Stacks For Statistical Leakage Characterization
Janakiraman Viraraghavan,
Bishnu Prasad Das, Bharadwaj Amrutur
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Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-resistant Secure IC Design
Srividhya Rammohan, Vijay Sundaresan, Ranga Vemuri
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“Industry Standards from Accellera”,
Shrenik Mehta,
Accellera Chair,
SUN Microsystems
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A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions
Sabyasachi Das,
Sunil P. Khatri
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Self-Sleep Buffer for Distributed MTCMOS Design
Charbel J. Akl,
Magdy A. Bayoumi
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Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier
Chester Rebeiro,
Debdeep Mukhopadhyay |
“IEEE Market-Oriented Standards Process and the EDA Industry”,
Dennis Brophy, Accellera-Vice Chair, Mentor Graphics
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Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis
Vyas Krishnan,
Srinivas Katkoori
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Power Management of Interactive 3D-Games using Frame Structures
Yan Gu,
Samarjit Chakraborty
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Throughput efficient Parallel Implementation of SPIHT algorithm
Anilkumar V. Nandi, R.M.Banakar |
“Design Automation Standards the IP providers perspective”
John Goodenough, ARM |
On the Use of Hash Tables for Efficient Analog Circuit Synthesis
Almitra Pradhan,
Ranga Vemuri |
Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations
Bishnu Prasad Das, Bharadwaj Amrutur, H.S. Jamadagni,
N.V. Arvind |
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“Driving Analog Mixed Signal Verification through Verilog-AMS”,
Sri Chandra, Freescale |
An Inversion-Based Synthesis Approach for Area and Power efficient Arithmetic Sum-of-Products
Sabyasachi Das,
Sunil P. Khatri
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Watermarking Video Clips with Workload Information: A New Approach to DVS
Yicheng Huang, Samarjit Chakraborty, Ye Wang |
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“VSI Standards, Current Status and Future Work”
Kathy Werner, Freescale |
| Lunch |
Plenary Talk
Emerging Technologies for Information and Signal Processing
Speaker: Dr. Pinaki Mazumder
Program Director, Emerging Models and Technologies, National Science Foundation |
The EKA Supercomputer: Plenary Session
Talk 1:
Title: Supercomputers: The Eka Experience Speaker: Dr. Sunil Sherlekar, TCS
Talk 2: Title: Anatomy of the Eka Supercomputer Speaker: Dr. N. Seetha Rama Krishna, TCS
Talk 3: Title: Applications of Supercomputing to Nanoelectronics Speaker: Dr. Rajendra Patrikar, TCS
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PANEL
Topic: Industry Needs versus VLSI Education in India
Moderator: Dr. C.P. Ravikumar, Texas Instruments, India
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| Technical Exhibition and Industry Forum |
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Leading EDA and IT companies will display their products from 9:00 am to 5:00 pm during January 6-8, 2008. Vendor presentations and panel discussion on industry will be held in a separate parallel track during the above three days. |
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