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  Tutorial Program :

 
World-renowned experts will offer eight high-quality, full-day tutorials as part of the conference on January 4 & 5, 2008. All tutorials will run from 9:00 AM to 5:00 PM, with a 1-hour lunch break at 12.30 pm and two 30-minute tea breaks at 10:30 am and 3:00 pm. One must register for tutorials separately. Tutorial Registration information is available at Registration.
  
 
Tutorials: January 4, 2008 (Friday)  
9:00 -10:30 AM  Session T1 Session T2 Session T3 Session T4A
Gateway to Chips : High Speed I/O Signalling and Interface
  • Nidhir Kumar, ARM Embedded Technologies.
  • Senthil N. Velu, ARM Embedded Technologies .
  • Rajan Verma, ARM Embedded Technologies.
DFM / DFT / SiliconDebug / Diagnosis

  • Nagesh Tamarapalli, AMD India Design Center.
  • Srikanth Venkataraman, Intel Corporation.
    		•
    Oversampling Analog-to-Digital Converter Design
    • Shanthi Pavan, IIT, Madras.
    • Nagendra Krishnapura , IIT, Madras.
    Programming and Performance Modelling of Automotive ECU Networks

  • Samarjit Chakraborty , National University of Singapore
  • S. Ramesh, General Motors R&D, India Science Laboratory, Bangalore
    • 10:30 - 11:00 AM Morning Tea Coffee
    11:00 - 12:30 PM
    Gateway to Chips : High Speed I/O Signalling and Interface
    • Nidhir Kumar, ARM Embedded Technologies.
    • Senthil N. Velu, ARM Embedded Technologies .
    • Rajan Verma, ARM Embedded Technologies.
    DFM / DFT / SiliconDebug / Diagnosis

  • Nagesh Tamarapalli, AMD India Design Center.
  • Srikanth Venkataraman, Intel Corporation.
    		•
    Oversampling Analog-to-Digital Converter Design
    • Shanthi Pavan, IIT, Madras.
    • Nagendra Krishnapura , IIT, Madras.
    Programming and Performance Modelling of Automotive ECU Networks

  • Samarjit Chakraborty , National University of Singapore
  • S. Ramesh, General Motors R&D, India Science Laboratory, Bangalore
    • 12:30 - 01:30 PM Lunch
    01:30 - 03:00 PM Session T1 Session T2 Session T3 Session T4B
    Gateway to Chips : High Speed I/O Signalling and Interface
    • Nidhir Kumar, ARM Embedded Technologies.
    • Senthil N. Velu, ARM Embedded Technologies .
    • Rajan Verma, ARM Embedded Technologies.
    DFM / DFT / SiliconDebug / Diagnosis

  • Nagesh Tamarapalli, AMD India Design Center.
  • Srikanth Venkataraman, Intel Corporation.
    		•
    Oversampling Analog-to-Digital Converter Design
    • Shanthi Pavan, IIT, Madras.
    • Nagendra Krishnapura , IIT, Madras.
    Architecture Exploration for Low Power Design

  • Vinod Kathail, Synfora, Inc.
  • Tom Miller, Sequence Design, Inc.
    		•
    03:00 - 03:30 PM Afternoon Tea
    03:30 - 05:00 PM
    Gateway to Chips : High Speed I/O Signalling and Interface
    • Nidhir Kumar, ARM Embedded Technologies.
    • Senthil N. Velu, ARM Embedded Technologies .
    • Rajan Verma, ARM Embedded Technologies.
    DFM / DFT / SiliconDebug / Diagnosis

  • Nagesh Tamarapalli, AMD India Design Center.
  • Srikanth Venkataraman, Intel Corporation.
    		•
    Oversampling Analog-to-Digital Converter Design
    • Shanthi Pavan, IIT, Madras.
    • Nagendra Krishnapura , IIT, Madras.
    Architecture Exploration for Low Power Design

  • Vinod Kathail, Synfora, Inc.
  • Tom Miller, Sequence Design, Inc.
    		•
     
    Tutorials: January 5, 2008 (Saturday)  
     
    9:00 -10:30 AM  Session T1 Session T2 Session T3 Session T4A
    Memory Design and Advanced Semiconductor Technology
    • D. Harame, S.S. Iyer, J.S. Watts, R. Joshi, and J.E. Barth Jr., IBM
    Scan Delay Testing of Nanometer SoCs
    • Adit D. Singh, Auburn University
    Cross-Layer Approaches to Designing Reliable Systems using Unreliable Chips
  • Fadi Kurdahi, UCI
  • Nikil Dutt, UCI
  • Ahmed Eltawil, UCI
  • Sani Nassif, IBM
    		•
    OpenSPARC - A scalable Chip Multi-Threading Design
  • Dwayne Lee, Sun Microsystems, Inc.
    • 10:30 - 11:00 AM Morning Tea Coffee
    11:00 - 12:30 PM
    Memory Design and Advanced Semiconductor Technology
    • D. Harame, S.S. Iyer, J.S. Watts, R. Joshi, and J.E. Barth Jr., IBM
    Scan Delay Testing of Nanometer SoCs
    • Adit D. Singh, Auburn University
    Cross-Layer Approaches to Designing Reliable Systems using Unreliable Chips
  • Fadi Kurdahi, UCI
  • Nikil Dutt, UCI
  • Ahmed Eltawil, UCI
  • Sani Nassif, IBM
    		•
    OpenSPARC - A scalable Chip Multi-Threading Design
  • Dwayne Lee, Sun Microsystems, Inc.
    • 12:30 - 01:30 PM Lunch
    01:30 - 03:00 PM Session T1 Session T2 Session T3 Session T4B
    Memory Design and Advanced Semiconductor Technology
    • D. Harame, S.S. Iyer, J.S. Watts, R. Joshi, and J.E. Barth Jr., IBM
    Scan Delay Testing of Nanometer SoCs
    • Adit D. Singh, Auburn University
    Cross-Layer Approaches to Designing Reliable Systems using Unreliable Chips

  • Fadi Kurdahi, UCI
  • Nikil Dutt, UCI
  • Ahmed Eltawil, UCI
  • Sani Nassif, IBM
    		•
    Implementing the Best Processor Cores

  • Vamsi Boppana, Technology Open-Silicon, Inc., CA
  • Rahoul Varma, Manager, ARM Embedded Technologies, Bangalore
  • S. Balajee, Texas Instruments India, Bangalore
    • 03:00 - 03:30 PM Afternoon Tea
    03:30 - 05:00 PM
    Memory Design and Advanced Semiconductor Technology
    • D. Harame, S.S. Iyer, J.S. Watts, R. Joshi, and J.E. Barth Jr., IBM
    Scan Delay Testing of Nanometer SoCs
    • Adit D. Singh, Auburn University
    Cross-Layer Approaches to Designing Reliable Systems using Unreliable Chips

  • Fadi Kurdahi, UCI
  • Nikil Dutt, UCI
  • Ahmed Eltawil, UCI
  • Sani Nassif, IBM
    		•
    Implementing the Best Processor Cores

  • Vamsi Boppana, Technology Open-Silicon, Inc., CA
  • Rahoul Varma, Manager, ARM Embedded Technologies, Bangalore
  • S. Balajee, Texas Instruments India, Bangalore
    •  
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