A1.1 Random Access Analog Memory (RA2M) for video signal application

Nilanjan Chattaraj and Anindya Sundar Dhar

IISc Bangalore

B1.1 Customizing Instruction Set Extensible Reconfigurable Processors using GPUs

Unmesh D. Bordoloi, Bharath Suri, Swaroop Nunna, Samarjit Chakraborty, Petru Eles and Zebo Peng

Linköping University, TU Munich

C1.1 Impact of Body Bias Based Leakage Power Reduction on Soft Error Rate

Warin Sootkaneung and Kewal K. Saluja

University of Wisconsin-Madison

A1.3A 110-dB Dynamic Range, 76-dB Peak SNR Companding Continuous-Time Delta Sigma Modulator for Audio Applications

Saravana Kumar and Shouri Chatterjee

Analog Devices Inc, IIT Delhi

B1.3 Intra-task Dynamic Cache Reconfiguration

Hadi Hajimiri and Prabhat Mishra

University of Florida

C1.3 An Energy Efficient Oscillator Frequency Calibration Methodology using Fraction Phase Computation

Amitava Ghosh, Isha Das and Achintya Halder

IIT Kharagpur

A2.1 Self-Induced Supply Noise Reduction Technique in GBPS rate Transmitters

Nitin Gupta, Tapas Nandy and Phalguni Bala

STMicroelectronics Pvt Ltd

B2.1 HD Resolution Intra Prediction Architecture for H.264 Decoder

Jimit Shah, Komanduri S. Raghunandan and Kuruvilla Varghese

IISc Bangalore

C2.1 Bidirectional Single-Supply Level Shifter with Wide Voltage Range for Efficient Power Management.

Sujan Manohar, Vinod Somasundar, Ramakrishnan Venkatasubramanian and Poras Balsara

University of Texas at Dallas

A2.2 Buffer Design and Eye-Diagram Based Characterization of a 20 GS/s CMOS DAC

Mohit Singh and Shalabh Gupta

IIT Bombay

B2.2 Design for Security of Block Cipher S-Boxes to Resist Differential Power Attacks

Bodhisatwa Mazumdar, Debdeep Mukhopadhyay and Indranil Sengupta

IIT Kharagpur

A2.3 Analog Processing Based Equalizer for 40 Gbps Coherent Optical Links in 90 nm CMOS

Pawan Kumar Moyade, Nandakumar Nambath, Allmin Ansari and Shalabh Gupta

IIT Bombay

B2.3 Real-time Melodic Accompaniment System for Indian Music Using TMS320C6713

Prateek Verma and Preeti Rao

IIT Bombay

A3.1 3-D Parasitic Modeling for Rotary Interconnects

Vinayak Honkote, Ankit More and Baris Taskin

Drexel University

B3.1 GPU Implementation of a Programmable Turbo Decoder for Software Defined Radio Applications

Dhiraj Reddy Nallapa Yoge and Nitin Chandrachoodan

IIT Madras

C3.1 Run-time Prediction of the Optimal Performance Point in DVS-based Dynamic Thermal Management

Junyoung Park, H. Mert Ustun and Jacob A. Abraham

University of Texas at Austin

A3.2 Power Aware Post-Manufacture Tuning of MIMO Receiver Systems

Debashis Banerjee, Shreyas Sen, Shyam Devarakond and Abhijit Chatterjee

Georgia Institute of Technology

C3.2 Temperature-aware Task Partitioning for Real-Time Scheduling in Embedded System

Zhe Wang, Sanjay Ranka and Prabhat Mishra

University of Florida

C3.3 Towards Thermal Profiling in CMOS/Memristor Hybrid RRAM Architectures

Cory Merkel and Dhireesha Kudithipudi

Rochester Institute of Technology

A4.1 CMOS Gas Sensor Array Platform with Fourier Transform based Impedance Spectroscopy

Pramod M, Navakanta Bhat, Gaurab Banerjee, Bharadwaj Amrutur, K N Bhat and Praveen C Ramamurthy

IISc Bangalore

B4.1 Low-Latency No-Handshake GALS Interfaces for Fast-Receiver Links

Jean Michel Chabloz and Ahmed Hemani

Royal Institute of Technology Stockholm

C4.1 An Integrated CMOS RF Energy Harvester with Differential Microstrip Antenna and On-Chip Charger

Mahima Arrawatia, Varish Diddi, Harsha Kochar, Maryam Shojaei Baghini and Girish Kumar

IIT Bombay

A4.2 A Compact Temperature Sensor at 1.8μA per Hz Conversion rate and 1.1 °C accuracy for SOCs

Subhajit Sen, Dan Babitch and Noshir Dubash

DAIICT Gandhinagar

B4.2 Set-Cover Heuristics for Two-Level Logic Minimization

Ankit Kagliwal and Shankar Balachandran

IIT Madras

C4.2 Low-Overhead Maximum Power Point Tracking for Micro-Scale Solar Energy Harvesting Systems

Chao Lu, Sang-Phill Park, Vijay Raghunathan and Kaushik Roy

Purdue University

A4.3 Analysis of the Pull-In phenomenon in Microelectromechanical Varactors

Anindya Lal Roy, Anirban Bhattacharya, Ritesh Ray Chaudhuri and Tarun Kanti Bhattacharyya

IIT Kharagpur

B4.3 A Rapid Methodology for Multi-mode Communication Circuit Generation

Liang Tang, Sri Parameswaran and Jorgen Peddersen

University of New South Wales

C4.3 Hybrid NEMS-CMOS DC-DC converter for improved area and power efficiency

Sujan Manohar, Ramakrishnan Venkatasubramanian and Poras Balsara

University of Texas at Dallas,Texas Instruments

A5.1 A Heuristic Method for Co-optimization of Pin Assignment and Droplet Routing in Digital Microfluidic Biochip

Ritwik Mukherjee, Hafizur Rahaman, Indrajit Banerjee, Tuhina Samanta, and Parthasarathi Dasgupta

BES University Shibpur, IIM Calcutta

B5.1 Real-Time, Content Aware Camera–Algorithm–Hardware Co-Adaptation for Minimal Power Video Encoding

Joshua Wells, Jayaram Natarajan, Abhijit Chatterjee and Irtaza Barlas

Georgia Institute of Technology, Impact Technologies

C5.1 A Novel Encoding scheme for Low Power in Network on Chip links

Deepa N Sarma

NIT Trichy

A5.2 Clock Tree Skew Minimization with Structured Routing

Pinaki Chakrabarti

Synopsys India Pvt Ltd

C5.2 A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage Islands

Nishit Kapadia and Sudeep Pasricha

Colorado State University

A5.3 Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology

Sourindra Chaudhuri, Prateek Mishra and Niraj Jha

Princeton University

C5.3 An Ultra-low Power Symbol Detection Methodology and Its Circuit Implementation for a Wake-up Receiver in Wireless Sensor Nodes

Deepak Kumar Meher, Arunkumar Salimath and Achintya Halder

SanDisk India Bangalore, IIT Kharagpur

A6.1 A Framework for TSV Serialization-aware Synthesis of Application Specific 3D Networks-on-Chip

Sudeep Pasricha

Colorado State University

B6.1 Way Sharing Set Associative Cache Architecture

Janaraj C.J., Venkata Kalyan Tavva, Tripti Warrier and Madhu Mutyam

IIT Madras

C6.1 A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip

Praveen Salihundam, Asadullah Khan Mohammed, Shailendra Jain, Satish Yada, Shasi Kumar, Vasantha Erraguntla, Sriram Vangal, Yatin Hoskote and Nitin Borkar

Intel Corp

B6.2 Low Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs

Sai Phaneendra P, Chetan Vudadha, Goutham Makkena, Venkata Swamy Nayudu Mandala, Sreehari V, Ershad Ahmed S, Moorthy Muthukrishnan N and Srinivas M.B.

BITS-Pilani Hyderbad Campus

C6.2 Efficient Online RTL Debugging Methodology for Logic Emulation Systems

Somnath Banerjee and Tushar Gupta

Mentor Graphics Pvt Ltd India

B6.3 A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS

Raguram Damodaran, Timothy Anderson, Sanjive Agarwala, Rama Venkatasubramanian, Michael Gill, Dhileep Gopalakrishnan, Abhijeet Chachad, Dheera Balasubramanian, Naveen Bhoria, Jonathan Tran, Duc Bui, Mujibur Rahman, Shriram Moharil, Matthew Pierson, Steve Mullinnix, Hung Ong, David Thompson, Krishna Gurram, Oluleye Olorode and Nuruddin Mahmood

Texas Instruments Inc Dallas

C6.3 SCARE: Side-Channel Analysis based Reverse Engineering for Post-Silicon Validation

Xinmu Wang, Seetharam Narasimhan, Aswin Krishna and Swarup Bhunia

Case Western Reserve University

A7.1 Kriging-Assisted Ultra-Fast Simulated-Annealing Optimization of a Clamped Bitline Sense Amplifier

Oghenekarho Okobiah, Saraju Mohanty, Elias Kougianos and Oleg Garitselov

University of North Texas

B7.1 Synthesis of Reversible Circuits using Heuristic Search Method

Kamalika Datta, Gaurav Rathi, Indranil Sengupta and Hafizur Rahaman

BES University, IIT Kharagpur

C7.1 Eliminating Performance Penalty of Scan

Ozgur Sinanoglu

New York University - Abu Dhabi

A7.2 Fast-Accurate Non-Polynomial Metamodeling for nano-CMOS PLL Design Optimization

Oleg Garitselov, Saraju Mohanty and Elias Kougianos

University of North Texas

B7.2 Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis

Sajib Mitra and Ahsan Raja Chowdhury

University Of Dhaka

C7.2 A Silicon Testing Strategy for Pulse-Width Failures

Srinivas Vooka, Pranav Murthy, Khushboo Agarwal, Venkatraman Ramakrishnan and Abhijeet Shrivastava

Texas Instruments India Pvt Ltd

A7.3 Circuit Optimization at 22nm Technology Node

Angada Sachid, Pallavi Paliwal, Sanjay Joshi, Maryam Shojaei, Dinesh Sharma and V. Ramgopal Rao

University of California Berkeley, IIT Bombay

B7.3 Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory

Somnath Paul, Lei Wang and Swarup Bhunia

Case Western Reserve University

C7.3 At-speed Testing of Asynchronous Reset De-assertion Faults

Arvind Jain, Srinivas Vooka, Neeraj Pradhan, Prasun Nair and Maheedhar Jalasutram

Texas Instruments, BITS-Pilani Goa Campus

A8.1 A Library for Passive Online Verification of Analog and Mixed-Signal Circuits

Debjit Pal, Pallab Dasgupta and Siddhartha Mukhopadhyay

IIT Kharagpur

C8.1 Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation

Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Sudhakar Reddy and Bernd Becker

University of Freiburg, University of Iowa

A8.2 A Fast Equation Free Iterative Approach to Analog Circuit Sizing

Supriyo Maji and Pradip Mandal

IIT Kharagpur

B8.1 Design Contest Presentation (DC):Hardware Architecture for pairwise Statistical Significance Estimation in Bioinformatics Problems

Daniel Honbo ; Alok Choudhary Northwestern University, Amit Pande,Northwestern University,Ankit Agrawal

C8.2 Formal Verification of Galois Field Multipliers using Computer Algebra Techniques

Jinpeng LV and Priyank Kalla

University of Utah

A8.3 Iterative Performance Model Upgradation in Geometric Programming based Analog Circuit Sizing for Improved Design Accuracy

Samiran Dam and Pradip Mandal

IIT Kharagpur

Design Contest Winner Hardware Architecture for Pairwise Statistical Significance Estimation in Bioinformatics Problems

Daniel Honbo, Amit Pande, Ankit Agrawal and Alok Choudhary

Northwestern University, University of California Davis

C8.3 A Novel SMT-Based Technique for LFSR Reseeding

Sarvesh Prabhu, Michael Hsiao, Loganathan Lingappan and Vijay Gangaram

Virginia Tech, Intel Corp

A9.1 Two Graph based Circuit Simulator for PDE-Electrical Analogy

Yogesh Save, H. Narayanan and Sachin Patkar

IIT Bombay

B9.1 Hardware Efficient Architecture for Generating Sine/Cosine Waves

Supriya Aggarwal and Kavita Khare

NIT Bhopal

C9.1 A Diagnosability Metric for Test Set Selection targeting better Fault Detection

Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta and Rohit Kapur

IIT Kharagpur, Synopsys

A9.2 Modeling of Partially Depleted SOI DEMOSFETs With a Sub-circuit Utilizing the HiSiM-HV Compact Model.

Tarun Kumar Agarwal and M. Jagadesh Kumar

IIT Delhi

B9.2 Power Aware Hardware Prototyping of Multiclass SVM Classifier

Rajesh Patil, Gauri Gupta, Vineet Sahula and Atanendu Mandal

MNIT Jaipur, CEERI Pilani

C9.2 Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias

Breeta Sengupta, Urban Ingelsson and Erik Larsson

Linköping University

A9.3 Implications of halo implant shadowing and backscattering from mask layer edges on device leakage current in 65nm SRAM

Srinivasaiah H. C

Dayananda Sagar College of Engineering Bangalore

B9.3 A High Speed FIR filter Architecture based on Novel Higher Radix Algorithm

Sahoo SK and Srinivasa Reddy K

BITS-Pilani

C9.3 Externally Tested Scan Circuit With Built-In Activity Monitor and Adaptive Test Clock

Priyadharshini Shanmugasundaram and Vishwani Agrawal

NVIDIA, Auburn University