Title: A History of the VLSI Design Conference

Abstract:

In December 1985, a group of about eighty-five assembled on the campus of the Indian Institute of Technology in Chennai for the First International Workshop on VLSI Design. The sole purpose of that meeting was to sense the level of VLSI activities in India. We were looking for a focus for engineering education and research. We felt that VLSI technology will be an area of progress in the coming years. The workshop was concluded with great enthusiasm but with no plan for the future. Therefore, it was no surprise that no workshop was held in the following year or the year after. The Second and Third Workshops were held, with some difficulties, in 1988 and 1990, respectively. Fortunately, those initial workshops created enough synergy to get the ball rolling. They spun off their own sponsoring society, the VLSI Society of India. Today, the International Conference on VLSI Design has come a long way to become a conference with world-wide recognition. This talk traces the history of the conference, its beginning, the struggling years, successes, failures and some groundbreaking contributions that made it what it is today.

Speaker Biography

Vishwani D. Agrawal is the James J. Danaher Professor of Electrical and Computer Engineering at Auburn University, Alabama, USA. He has over forty years of industry and university experience, working at Bell Labs, Murray Hill, NJ; Rutgers University, New Brunswick, NJ; TRW, Redondo Beach, CA; IIT, Delhi, India; EG&G, Albuquerque, NM; and ATI, Champaign, IL. His areas of work include VLSI testing, low-power design, and microwave antennas. He obtained his BE degree from the University of Roorkee (renamed Indian Institute of Technology), Roorkee, India, in 1964; ME degree from the Indian Institute of Science, Bangalore, India, in 1966; and PhD degree in electrical engineering from the University of Illinois, Urbana-Champaign, in 1971. He has published over 300 papers, has coauthored five books and holds thirteen United States patents. His textbook, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, co-authored with M. L. Bushnell, was published in 2000. He is the founder and Editor-in-Chief (1990-) of the Journal of Electronic Testing: Theory and Applications, past Editor-in-Chief (1985-87) of the IEEE Design & Test of Computers magazine and a past Editorial Board Member (2003-08) of the IEEE Transactions on VLSI Systems. He is the Founder and Consulting Editor of the Frontiers in Electronic Testing Book Series of Springer. He is a co-founder of the International Conference on VLSI Design, and the VLSI Design and Test Symposium, held annually in India.  He was the invited Plenary Speaker at the 1998 International Test Conference, Washington D.C., and the Keynote Speaker at the Ninth Asian Test Symposium, held in Taiwan in December 2000. During 1989 and 1990, he served on the Board of Governors of the IEEE Computer Society, and in 1994, chaired the Fellow Selection Committee of that Society. He has received eight Best Paper Awards and two Honorable Mention Paper Awards. In 2006, he received the Lifetime Achievement Award of the VLSI Society of India, in recognition of his contributions to the area of VLSI Test and for founding and steering the International Conference on VLSI Design in India. In 1998, he received the Harry H. Goode Memorial Award of the IEEE Computer Society, for innovative contributions to the field of electronic testing, and in 1993, received the Distinguished Alumnus Award of the University of Illinois at Urbana-Champaign, in recognition of his outstanding contributions in design and test of VLSI systems. Dr. Agrawal is a Fellow of the IETE-India (elected in 1983), a Fellow of the IEEE (elected in 1986) and a Fellow of the ACM (elected in 2003). He has served on the advisory boards of the ECE Departments at University of Illinois, New Jersey Institute of Technology, and the City College of the City University of New York. See his website http://www.eng.auburn.edu/~vagrawal

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Title: A wireless sensor a day keeps the doctor away

Abstract:

Chronic diseases are predicted to be the leading cause of disability, and will become the most expensive problem affecting all countries (source: WHO). Many of these chronic diseases can be prevented, but this requires a paradigm shift to integrated and preventive healthcare (source: WHO). The focus of future healthcare systems should be on keeping people healthy, raising each individual¹s awareness on his own health and inducing efficient behavioral changes. The patient of the future is a healthy patient. Wearable sensors are instrumental in managing chronic conditions, providing real-time diagnostics and patient-centric therapies.

In this talk we will review recent technology breakthroughs in wireless sensors, and demonstrate their impact in a few pilot studies. New micro-electronic technologies lead to miniaturized low-power wireless

Speaker Biography

Bert Gyselinckx combines his role as Human++ program director with that of general manager of imec at the Holst Centre. Human++ is pioneering a unique open‐innovation ecosystem in the field of wireless sensors for healthcare and lifestyle. As a result, today over 200 scientific staff and a dozen of residents from industrial partner companies are creating groundbreaking future generation healthcare, lifestyle and life science solutions. In his early career, Bert made pioneering contributions to wireless OFDM communications that were the seed for a couple of startup companies leading to our current generation of WiFi modems.
Bert lives by the golden rule “working hard, playing hard”. In 2001, he replaced his office chair for a bike saddle and went on a 12 month odyssey in the Asia Pacific region. 15000km later, he was inspired to create technologies that can have a true impact on society. Bert received the M.S. degree in Electrical Engineering from the Rijksuniversiteit Gent, Belgium, in 1992 and the M.S. degree in Air and Space Electronics from the Ecole Nationale Superieure de l'Aeronautique et de l'Espace, Toulouse, France, in 1993. At this time, he was also a trainee at the Research and Development group of Siemens in Munich, Germany.

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Title: India's Golden Age of Electronics: The Best is Yet to Come

Abstract:

Best of times: Semiconductors have been at the heart of most technological progress in the past few decades and have had a profoundly positive impact on the human condition. It is hard to argue when many say that we are living in the “golden age of electronics”. Human ingenuity has enabled the creation of products that customers never asked for, but now cannot live without - everything from computers to digital cameras, mp3 players and mobile phones. The most successful products and applications are the creative use and convergence of technologies and application domains. Truly speaking, this is only the beginning. The consumerization of electronics, globalization of markets and the human aspiration for a better quality of life is creating unprecedented opportunities that only the semiconductor industry can help realize.

Worst of times: 2008 was an inflexion point in the global economic boom we witnessed since the dot-com bubble burst earlier in the millennium. Across the board, businesses are still struggling to grow and constantly looking at opportunities to improve operational efficiencies. Unemployment in the developed world is at a multi-decade high and GDP growth rates at a multi-year low. We are yet to feel the full impact of the economic down-turn, and the social impact that will follow has not even really started. One thing is certain, this is not a transitory phase; this is the new normal.

Nowhere else I would rather be: The next wave of economic growth will stem from integrating the people who belong to the “base-of-the-economic-pyramid” into the formal economy and dramatically improving their productivity. There are limitless possibilities and opportunities that exist for the semiconductor industry to continue to be a key driver to improve the human condition further over the next several decades. It is still the best place to be, and the “golden age of electronics” has only just started.

Speaker Biography

Jaswinder S. Ahuja, 48, is Corporate Vice President and Managing Director of Cadence Design Systems in India. Jaswinder leads Cadence’s India Operating Region which includes R&D, Sales, Technical Field Operations, Marketing, Services, Global Support and Global IT.

Jaswinder is a founding member of VLSI Society of India and at present serves as its President. He was Chairman of the India Semiconductor Association in 2008-09 when he initiated the Electronic System Design and Manufacturing (ESDM) agenda for the industry. Jaswinder also serves on the board of advisors of FirstRain, Inc. and Zafesoft, Inc.

Jaswinder has a B.Tech in Electronics Engineering from IT-BHU, Varanasi and an MS in Computer Engineering from Northeastern University, Boston, USA. He also holds an Executive MBA from Stanford University, USA.

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Title: Emerging trends in Process Technologies

Speaker Biography

Mr. Jean Boufarhat is Corporate Vice President of Advanced Micro Devices Process and Circuit Technology. His responsibilities span Silicon Process Technology Enablement, Memory Array, High-Speed IO and Analog/Mixed-Signal Design. Prior to his current role, Mr. Boufarhat was responsible for ASIC Services and Technology for the Graphic Products Division. Prior to joining AMD in 2007, Mr. Boufarhat spent ten years at LSI where he was Vice President of IP Solutions. Before his last role at LSI, Mr. Boufarhat held various management positions in IP development, high-speed mixed-signal design and design methodology. Before joining LSI, Mr. Boufarhat held various engineering and management positions at Symbios, AT&T and NCR. Mr. Boufarhat has B. Sc. and M. Sc. Degrees in electrical engineering from the University of North Carolina at Charlotte.

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Title: The Variability Expeditions: Exploring the Software Stack for Underdesigned Computing Machines

Abstract:

As microelectronic devices scale down to the level molecular assemblies the resulting circuits and systems do not behave like the precisely chiseled machines with tight tolerances. Modern computing is ignorant of the variability in the behavior of underlying components from device to device, chip to chip, its wear over time, or the environment in which the computing system is placed. The 'guardbands' used to guarantee component behavior (for power, performance) have gone to ridiculous margins accounting for as much as two-thirds of the chip area to meet performance 'specs' and is already undermining the gains from continued device scaling. Changing the way software interacts with hardware offers the best hope to recover the advantages from process scaling. In this talk I will describe our approach and progress in the Variability Expeditions project that fundamentally rethinks the rigid, deterministic hardware-software interface, to propose a new class of computing machines that rely on an opportunistic software stack to adapt to the conditions in an underdesigned hardware.

Speaker Biography

Rajesh K. Gupta is a professor and chair of Computer Science and Engineering at UC San Diego, and holds the QUALCOMM endowed chair. His research interests are in energy efficient systems that have taken turn towards large-scale energy use in recent years. His recent contributions include SystemC modeling and SPARK parallelizing high-level synthesis, both of which are publicly available and have been incorporated into industrial practice. Earlier Gupta lead or co-lead DARPA-sponsored efforts under the Data Intensive Systems (DIS) and Power Aware Computing and Communications (PACC) programs that demonstrated architectural adaptation and compiler optimizations in building high performance and energy efficient system architectures. His ongoing efforts include energy-efficient data-centers and large scale computing using memory-coherent algorithmic accelerators and non-volatile storage systems. In recent years, Gupta and his students have received a best paper award at IEEE/ACM DCOSS’08 and a best demonstration award at IEEE/ACM IPSN/SPOTS’05. Gupta received a BTech in EE from IIT Kanpur, MS in EECS from UC Berkeley and a PhD in Electrical Engineering from Stanford University. He currently serves as EIC of IEEE Embedded Systems Letters. Gupta is a Fellow of the IEEE.

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Title: 15 billion by 2015 – Transformation of Embedded devices to Intelligent Systems

Abstract:

In the next five years, the number of embedded devices is set to explode from ~5 billion to ~15 billion and will sport key attributes of being connected, intelligent and power efficient. These devices will span a wide spectrum across in-vehicle infotainment, digital security and surveillance, industrial/home automation to portable medical devices and more.

The line between embedded devices, embedded systems, compute platforms and Cloud is already blurring driven by the end goal of delivering a rich user experience that transcends a particular device/platform and independent of location. A growing number of these embedded devices will evolve from simple unconnected, non-persistent entities to more intelligent systems with 'intelligence' residing in both the end devices as well reaching all the way into the Cloud. The ability to deliver end-user experience seamlessly across the device and reaching into the Cloud and back is commonly referred to as Compute Continuum.

This talk will address the transformation of embedded devices to intelligent systems and talk about the exciting requirements and challenges of delivering compute continuum. The talk will touch on specific examples in the auto, energy and consumer verticals to highlight instances of this transformation. This transformation of devices to intelligent systems also holds bountiful benefits in an emerging market context and the talk will highlight a few examples. Finally, we will tie the technological challenges and potential solutions to help accelerate the transformation of embedded systems to intelligence systems.

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Title: Challenges in Automotive Cyber-physical Systems Design

Abstract:

Systems with tightly interacting computational (cyber) units and physical systems are generally referred to as cyber-physical systems. They involve an interplay between embedded systems, control theory, real-time systems and software engineering. A very good example of cyber-physical systems design arises in the context of automotive architectures and software. Modern high-end cars have 50-100 processors or electronic control units (ECUs) that communicate over a network of buses such as CAN and FlexRay. In such complex settings, traditional control-theoretic approaches -- where control engineers are only concerned with high-level plant and controller models -- start breaking down. Instead it becomes necessary to adopt a more holistic, cyber-physical systems design approach where the semantic gap between high-level control models and their actual implementations on multiprocessor platforms is quantified and consciously closed. We will give several examples on how this may be done and the current research challenges facing both academia and the industry.

Speaker Biography

Samarjit Chakraborty is a professor of Electrical Engineering at TU Munich in Germany, where he heads the Institute for Real-Time Computer Systems (RCS). Prior to joining TU Munich, from 2003 - 2008 he was an Assistant Professor of Computer Science at the National University of Singapore. He obtained his Ph.D. in Electrical and Computer Engineering from ETH Zurich in 2003. His research interests cover all aspects of system-level design of real-time embedded systems and software, including automotive electronics and software, advanced automotive driver assistance systems, e-mobility and electric vehicles. In addition to his Chair at TU Munich, Prof. Chakraborty leads a research program on embedded systems design for electric vehicles, at the TUM CREATE Centre for Electromobility in Singapore, where he also serves as a Scientific Advisor.

Prof. Chakraborty has published over 100 articles in various top-tier research forums in the real-time and embedded systems domain, including DAC, DATE, CODES+ISSS, EMSOFT, ASP-DAC, RTSS and RTAS, and regularly serves on the technical program committees of many of these conferences. He has served as the general chair of the Embedded Systems Week (ESWeek) 2011, was one of the general chairs of the 9th International Conference on Embedded and Ubiquitous Computing (EUC) 2011 and is a general chair of the IEEE International Symposium on Industrial Embedded Systems (SIES) 2012. He has also served as the technical program committee chair of the International Conference on Embedded Software (EMSOFT) 2009, and has been a Track/Topic Chair in several editions of DATE, ASP-DAC and RTSS.
For his Ph.D. thesis, he received the ETH Medal and the European Design and Automation Association's Outstanding Doctoral Dissertation Award in 2004. His work has also received Best Paper Awards at ASP-DAC 2011, EUC 2010, a HiPEAC Paper Award in 2009 and Best Paper Award nominations at EMSOFT 2010, CODES+ISSS 2008, ECRTS 2007, CODES+ISSS 2006, and DAC 2005.

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Title: Security and Reliability in Embedded Systems

Abstract:

Deep devastation is felt when privacy is breached, personal information is lost, or property is stolen. Now imagine that all of this can happen at once, and the victim is unaware of its occurrence until much later. This is the reality, as increasing amount of electronic devices are used as keys, wallets and files. Security attacks targeting embedded systems illegally gain access to information or destroy information. Such threats in embedded systems could be classified by the means used to launch attacks. Typical launch methods are physical, logical/software-based and side-channel/lateral attacks. Physical attacks refer to unauthorized physical access to the embedded system itself and are feasible only when the attacker has direct access to the system. Logical attacks exploit weaknesses in logical systems such as software or a cryptographic protocol to gain access to unauthorized information. Logical attacks are deployed easily against systems, which are able to download and execute software and have vulnerabilities in their design. Side-channel attacks are performed by observing properties of the system (such as power consumption, electromagnetic emission, etc.) while the system performs cryptographic operations.

A wide range of techniques has been proposed in the past to detect and counter security attacks in embedded devices. They could broadly be categorized into software-based techniques and hardware assisted techniques. Software based techniques use software tools such as code analysers and methods such as proof-carrying-code to overcome these attacks without changing the architecture of the processor. Hardware assisted techniques use additional hardware blocks or micro-architectural support to detect and protect against these security attacks. The talk gives an overview of the most popular attacks on embedded computing systems, and some countermeasures against logical and side-channel attacks.

Speaker Biography

Sri Parameswaran is a Professor in the School of Computer Science and Engineering at the University of New South Wales. He also serves as the Postgraduate Research and Scholarships coordinator at the same school. Prof. Parameswaran received his B. Eng. Degree from Monash University and his Ph.D. from the University of Queensland in Australia. He has held visiting appointments at University of California, Kyushu University and Australian National University. He also worked as a consultant to the NEC Research laboratories at Princeton, USA and to the Asian Development Bank. His research interests are in System Level Synthesis, Low power systems, High Level Systems, Network on Chips and Secure and Reliable Processor Architectures. He serves on the editorial boards of ACM Transactions on Embedded Computing Systems, the EURASIP Journal on Embedded Systems and the Design Automation of Embedded Systems. He has served on the Program Committees of Design Automation Conference (DAC), Design and Test in Europe (DATE), the International Conference on Computer Aided Design (ICCAD), the International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS), and the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES).

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Title: FPGA Roadmap:Technology Challenges & Transitioning to Stacked Silicon Interconnect.

Abstract:

FPGA logic capacity continues to double with successive process technology nodes, driven by Moore's Law, and this has enabled systems-on-chip (SOC) of greater complexity. As impressive as these gains have been, the market demands ever higher levels of integration and bandwidth. At the same time, the need for FPGAs with higher density of logic, DSP, memory and IOs must be met cost effectively. This talk will outline how we can meet these challenges. Xilinx has addressed these problems through the development of FPGA products using Stacked Silicon Interconnect (SSI) technology. SSI utilizes micro-bump and Through-Silicon Via (TSV) technologies, with multiple active die on a passive interposer to enable integration beyond what's possible with monolithic die or Multi-Chip Modules (MCMs). An overview of the technology, design and supply chain challenges will be given as well as potential future directions.

Speaker Biography

Suresh Menon is vice president of product development for the programmable platforms development group. He has responsibility for leading a centralized global organization responsible for FPGA architecture development for the flagship Virtex and Spartan programmable platforms.

Menon joined Xilinx in 1999 with more than 20 years experience in product design and engineering management. Previous to joining Xilinx, Menon was a founder at Dynachip Corp. where he served as vice president of field programmable gate array products. Menon began his career at Fairchild Semiconductor and later worked at Digital Equipment Corp. as a research engineer.

Menon holds a bachelor's degree in electrical and electronics engineering from the University of Aston, Birmingham, England. He holds more than 25 patents in analog and FPGA design.

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Title: The future of Semiconductor Design: What the India Electronics Industry can learn from Apple

Speaker Biography

Rajeev Madhavan has served as Magma's Chief Executive Officer and Chairman of the Board of Directors since he co-founded the company in 1997, and also served as president until 2001. Prior to founding Magma, he co-founded and served as President and CEO of Ambit Design Systems, Inc. and co-founded and served as Director of Engineering of LogicVision, Inc. Madhavan received a bachelor's degree in electronics and communication from KREC, Surathkal, India, and a master's degree in electrical engineering from Queen's University, Ontario, Canada

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