VLSI Design 2010
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  Tutorial Program
25th International Conference on VLSI Design
Two Full Day Tutorial Program Schedule
Day 1:  7 th January 2012
Time Session T1 Session T2 Session T3 Session T4
9AM - 5PM

Design of Mixed-Signal Systems using SystemC
AMS extensions

Sumit Adhikari1,  
Markus Damm1,
Christoph Grimm1 and François Pecheux2

1Vienna University of
Technology, Austria

2UPMC, Paris, France
Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future

Himanshu Thapliyal and Nagarajan Ranganathan

University of South Florida, USA
DFM, DFT, Silicon Debug and Diagnosis – The loop to ensure product yield

Nagesh Tamarapalli1 and Srikanth Venkataraman2

1AMD, India

2Intel, Oregon, USA
Intellectual Property Protection and Security in System on a Chip

Susmita Sur-Kolay1 and Swarup Bhunia2

1Indian Statistical Institute

2Case Western Reserve University, USA
Day 2:  8 th January 2012
Time Session T5 Session T6 Session T7A Session T8A
9AM - 5PM Advanced Analog-Mixed Signal System and Circuit Techniques

Pavan Hanumolu, Un-Ku Moon, and Terri Fiez

Oregon State University, USA
Variability-resistant Software and Hardware for Nano-Scale Computing

Nikil Dutt1,
Mani Srivastava2, Rajesh Gupta3, and Subhashish Mitra4

1UC Irvine, USA

2University of California, Los Angeles,USA

3University of California, San Diego, USA

Stanford University, USA
New Modeling Methodologies for Thermal Analysis of 3D ICs and Advanced Cooling Technologies of the Future
(9am – 12 noon)

Arvind Shridhar and David Atienza

EPFL Switzerland
Designing Silicon-Photonic Communication Networks for Manycore Systems
(9am – 12 noon)

Ajay Joshi

Boston University, USA
Session T7B Session T8B
Optimally Addressing Verification Constraint Complexity for Effective Functional Convergence
(1pm - 5pm)

Shankar Hemmady

Synopsys, USA
Wireless System Design and Systems Engineering Challenges
(1pm - 5pm)

Ravi Kishore B, Kameswara Rao B, and
Muralidhar Reddy B

HCL India
Tutorial Abstracts:

Session T1: Design of Mixed-Signal Systems using SystemC AMS extensions

Sumit Adhikari (Vienna University of Technology, Austria),
Markus Damm (Vienna University of Technology, Austria),
Christoph Grimm (Vienna University of Technology, Austria)
François Pecheux (UPMC, Paris, France)

7th January 2012 (9AM - 5PM)

Abstract: SystemC has become an accepted standard for design of HW/SW Systems at system level. How-ever, nowadays systems include more and more analog/RF components such as transceivers, sensor interfaces, or PLL. To enable design of such mixed-signal systems, OSCI has standardized AMS extensions for SystemC in 2010. In addition to the capabilities of SystemC for modelling multi-processor HW/SW systems, the AMS extensions enable modelling the behaviour of analog/RF parts, physical environment and digital signal processing methods.

The tutorial gives an introduction into SystemC AMS extensions. The introduction includes the language itself, some simple examples, use cases and (top-down) methodology for refinement of AMS systems, starting from an executable specification.

Speaker Bios

Mr. Sumit Adhikari completed Master of Technology from Indian Institute of Technology, Kharagpur. After working for several years with QualCore Logic Inc. and Austriamicrosystems AG, he joined ICT, TU Vienna on April 2010 as a scientist. He is also working as AMSWG member at OSCI, contributing towards standardization of SystemC AMS. His interest lies on ASP designing, DSP designing and modelling, development of analogue-mixed signal HDL. His domain expertise lies on Automotive sensor actuator systems, RF-Wireless systems, Industrial electronic systems and Instrumentation applications. He has authored several publications in analogue designing, high level analogue system designing and modelling.

Mr. Markus Damm studied Mathematics and Computer Science at the Goethe University in Frankfurt am Main in Germany. After that, he joined the Computer Engineering group of Prof. Waldschmidt in Frankfurt. Since 2006, he works in the Embedded Systems Group of Prof. Grimm at the Institute of Computer Technology (ICT) at the TU Vienna. He is part of the SystemC AMS working group. His research interest includes the coupling of transaction level models with SystemC AMS models, and applying transaction level concepts for the simulation of wireless communication.

Prof. Christoph Grimm works on the design and design methodology of embedded mixed-signal systems. He has authored more than 100 scientific publications. He is editor of the book "Languages for System Specification", Kluwer 2004 and co-author or contributor to many standards such as the "SystemC AMS" Language Reference Manual, or the standards IEEE 1076.1 (VHDL-AMS) and IEEE 1076.6 (VHDL-SIWG). In 2003, he was General Chair, and in 2005/6 Program Chair (AMS Topic) of the Forum on Specification and Design Languages, and vice chair of the OSCI SystemC-AMS WG and chairs the scientific advisory board of OVE. Since 2006 he is full professor for Embedded Systems at the Institute for Computer Technology, Vienna University of Technology. Web: https://www.ict.tuwien.ac.at/en/user/6

Prof. François Pêcheux is an associate professor in the UPMC/LIP6 Laboratory in Paris, France. He is responsible for the SystemC training activities of UPMC/LIP6. He also coordinated several French and European projects like TSC, ADAM and played an active role in SocLib, a library of interoperable models for Multi Processor SystemC on Chip modelling. From 1995 to 2002 François Pêcheux worked in the Laboratoire de Physique et Applications des Semiconducteurs in Strasbourg, France. He also joined the Ecole Nationale Supérieure de Strasbourg (ENSPS). He developed several computer-aided design tools and dedicated software for the efficient modelling of systems at the CNRS and participated in the development of some mixed-signal models for sub-micron devices, taking into account physical interaction with the direct environment. In September 2002, he joined the LIP6 Laboratory Integrated Systems Department at the UPMC. He is the author or co-author of multiple articles and conference contributions on (SystemC-based) IC design methodology for homogeneous and heterogeneous systems. He has introduced a new course at UPMC dedicated to the modelling and simulation of heterogeneous systems.

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Session T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future

Himanshu Thapliyal (University of South Florida, USA)
Nagarajan Ranganathan (University of South Florida, USA)

7th January 2012 (9AM - 5PM)

Abstract: Reversible logic is emerging as a promising computing paradigm with applications in ultra-low power nanocomputing and emerging nanotechnologies such as quantum computing, quantum dot cellular automata (QCA), optical computing, etc. Reversible circuits are similar to conventional logic circuits except that they are built from reversible gates. In reversible gates, there is a unique, one-to-one mapping between the inputs and outputs, not the case with conventional logic. In this tutorial, the speakers will introduce fundamentals of reversible logic and its promising applications in ultra-low power nanocomputing, fault testing and emerging nanotechnologies, as well as the current state of the art and challenges in future. In this presentation, first, a brief overview of reversible logic basics will be given. Next, the speakers will introduce basic reversible logic gates and the key metrics that need to be optimized in reversible logic design and synthesis. Reversible gates require constant ancilla inputs for reconfiguration of gate functions and garbage outputs that help in keeping reversibility. Thus, it is important to minimize parameters such as ancilla and garbage bits, quantum cost and delay in the design of reversible circuits. Next, the speakers will introduce a number of basic reversible gates used in design and a new reversible gate namely the TR gate (Thapliyal-Ranganathan) which has the unique structure that makes it ideal for the realization of arithmetic circuits such as adders, subtractors and comparators, efficient in terms of the parameters such as ancilla and garbage bits, quantum cost and delay. The design methodologies and a framework to synthesize reversible data path functional units, such as binary and BCD adders, subtractors, barrel shifters, binary comparators and floating point units will be presented. The objective behind the proposed design methodologies is to synthesize arithmetic and logic functional units optimizing key metrics such as ancilla inputs, garbage outputs, quantum cost and delay. Next, the speakers will present a set of methodologies for the design of reversible sequential circuits such as reversible latches, flip-flops and shift registers. Next, the application of reversible logic in online and offline testing of single as well as multiple faults in traditional and reversible nanoscale VLSI circuits is introduced. As reversible logic has applications in various emerging technologies such as quantum computing, quantum dot cellular automata, optical computing etc, thus this tutorial will also cover the introductory material on these emerging nanotechnologies. A brief overview will be presented of the design of low power circuits based on reversible computing paradigm such as split charge recovery logic (SCRL), reversible energy recovery logic (RERL), nmos reversible energy recovery logic (nRERL), r-MOS, etc. The tutorial will conclude with discussions on current state of the art, progress and future challenges, such as reversible programming languages, design of reversible CPU, and the open questions about the implementation technologies that could pave the way of ultra-low power nano-processor. In conclusion, this tutorial will touch on reversible logic having application in traditional CMOS for low power computing to non-classical computing domain such as quantum computing, QCA computing. etc.

Speaker Bios

Mr. Himanshu Thapliyal received the B.Tech. degree in Computer Engineering from G.B. Pant University, India, in 2004, and the M.S. degree in VLSI and embedded systems from IIIT Hyderabad, India, in 2006. He will obtain the Ph.D. degree in Computer Science and Engineering from University of South Florida, Tampa, in 2011. He has authored or coauthored more than 40 articles in refereed conferences and journals and is a co-owner of a U.S. patent issued recently. In 2009, he received the Distinguished Graduate Achievement Award from the Graduate and Professional Student Council at USF for outstanding research and academic achievement. In 2010, the IEEE Computer Society awarded him with the Richard E. Merwin Scholarship in recognition of his contributions to student chapter activities, academic achievement and for serving as a student ambassador. In 2011, he received 2010 UPE/CS Award for Academic Excellence from the Upsilon Pi Epsilon Honor Society for the Computing Sciences and the IEEE computer Society. His Ph.D. dissertation work on reversible logic has been featured in MIT Technology Review, ACM TechNews, New Scientist Magazine, insideHPC, Softpedia News, etc. He is currently serving as the IEEE Computer Society representative in IEEE GOLD. Web: http://www.cse.usf.edu/~hthapliy/

Prof. Nagarajan “Ranga” Ranganathan (S’81-M’88-SM’92-F’02) received the B.E. (Honors) degree in Electrical and Electronics Engineering from Regional Engineering College (National Institute of Technology) Tiruchirapalli, University of Madras, India, 1983, and the Ph.D. degree in Computer Science from the University of Central Florida, Orlando in 1988. He is a Distinguished University Professor of Computer Science and Engineering at the University of South Florida, Tampa. During 1998-99, he was a Professor of Electrical and Computer Engineering at the University of Texas at El Paso. His research interests include VLSI circuit and system design, VLSI design automation, multi-metric optimization in hardware and software systems, computer architecture, and parallel computing. He has developed many special purpose VLSI circuits and systems for computer vision, image and video processing, pattern recognition, data compression and signal processing applications. He has co-authored over 275 papers in refereed journals and conferences, four book chapters and co-owns seven U.S. patents and one pending. He has edited three books titled VLSI Algorithms and Architectures: Fundamentals, VLSI Algorithms and Architectures: Advanced Concepts, IEEE CS Press, 1993, VLSI for Pattern Recognition and Artificial Intelligence, World Scientific Publishers, 1995 and co-authored a book titled, Low Power High Level Synthesis for Nanoscale CMOS Circuits, Springer, June 2008.
Dr. Ranganathan was elected as a Fellow of IEEE in 2002 for his contributions to algorithms and architectures for VLSI systems. He is a member of the IEEE, IEEE Computer Society, IEEE Circuits and Systems Society and the VLSI Society of India. He has served on the editorial boards for the journals: Pattern Recognition (1993-97), VLSI Design (1994-present), IEEE Transactions on VLSI Systems (1995-97), IEEE Transactions on Circuits and Systems (1997-99), IEEE Transactions on Circuits and Systems for Video Technology (1997-00), IEEE Transactions on Computers (2008-10), IEEE Transactions on CAD (2008-10) and ACM Transactions on Design Automation of Electronic Systems (2007-09). He was the chair of the IEEE Computer Society Technical Committee on VLSI during 1997-01. He is on the steering committee of the IEEE Transactions on VLSI Systems during 1999-01, 2007-present and the steering committee chair during 2002-03 and the Editor-in-Chief for two consecutive terms during 2003-06. He served as the program co-chair for ICVLSID’94, ISVLSI’96, ISVLSI’05, and ICVLSID’08 and as general co-chair for ICVLSID’95, IWVLSI’98, ICVLSID’98, ISVLSI’05 and ISVLSI’09. He has served on technical program committees of international conferences including ICVLSID, ICCD, ICPP, IPPS, SPDP, ICHPC, HPCA, GLSVLSI, ASYNC, ISQED, ISLPED, CAMP, ISCAS, MSE, DATE and ICCAD. Dr. Ranganathan received the USF Outstanding Research Achievement Award in 2002, USF President's Faculty Excellence Award in 2003, USF Theodore-Venette Askounes Ashford Distinguished Scholar Award in 2003, the SIGMA XI Scientific Honor Society Tampa Bay Chapter Outstanding Faculty Researcher Award in 2004, and the Distinguished University Professor honorific title and the university gold medallion honor in 2007, and the USF Outstanding Undergraduate Teaching Award in 2008. He was a co-recipient of three Best Paper Awards at the Intl. Conf. on VLSI Design in 1995, 2004 and 2006 and the IEEE Circuits and Systems Society VLSI Transactions Best Paper Award in 2009. He has been appointed as the Faculty Liaison for the University of South Florida Board of Trustees for the term 2011-2014. Web: http://www.cse.usf.edu/~ranganat/

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Session T3: DFM, DFT, Silicon Debug and Diagnosis – The loop to ensure product yield

Nagesh Tamarapalli (AMD, India)
Srikanth Venkataraman (Intel, Oregon, USA)

7th January 2012 (9AM - 5PM)

Semiconductor yield has traditionally been limited by random particle-defect based issues. However, as the feature sizes reduced to 90nm and below, systematic mechanism-limited yield loss began to appear as a substantial component in yield loss. In addition, it is becoming clear that ramping yield would take longer and final yields would not reach historical norms. A key factor for not reaching previously attained yield levels is the interaction between design and manufacturing. Yield losses in the newer processes include functional defects, parametric defects and issues with testing. Each of these sources of yield loss needs to be analyzed and understood by designers and tool developers. In addition, new techniques and methods must be devised to minimize the impact of these yield loss mechanisms. After an introduction of the issues involved in the first section, the second section covers Design-for-Manufacturing (DFM) techniques to analyze the design content, flag areas of design that could limit yield, and make changes to improve yield. However, once the changes are made it is necessary to quantify their impact so that knowledge about yield contribution of different features can be fed back to design and DFM tools. Test presents an opportunity to close the loop by crafting test patterns to expose the defect prone features during automatic test pattern generation (ATPG) and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield loss and their relative impact. The third section covers design techniques (DFX) to improve testability, debuggability and diagnosability, and DFM and defect-aware test generation to both meet product quality and expose yield issues at test. Section four covers the basic concepts and theoretical aspects of debug and diagnosis including algorithmic IC diagnosis, scan chain diagnosis, critical path based techniques and diagnosis of delay defects. The applications of the basic concepts and techniques for silicon debug are covered in section five. Section six covers the application of statistical diagnosis techniques to determine the features that are actually causing yield loss and their relative impact. Finally, in section seven, future trends, challenges and directions are covered.

The proposed tutorial includes the basics to be of interest to students, new engineers and managers but covers new and recent advances in hot topics in Design-for-Manufacturing, yield, test and diagnosis to be of interest to researchers and practicing engineers. The selection of topics cover a broad spectrum and will be of interest to a wide audience including design, test, product, validation, yield, debug and FA engineers.

Speaker Bios

Dr. Srikanth Venkataraman is a Principal Engineer at Intel Corporation in Hillsboro, OR. He manages an R&D group responsible for developing CAD tools for diagnosis, debug and test quality applications in the Design and Technology Solutions group. He has successfully developed and deployed several tools in test and diagnosis used all across Intel. His research interests include the areas of VLSI Test (product design for testability and test CAD), Fault diagnosis, Design Verification and Debug, CAD for VLSI, S/W Engineering and Development. He received his Ph.D. in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign. He has worked at Texas Instruments and ViewLogic Systems (Sunrise Test System). He has over 60 publications, 3 patents issued and 2 patents pending. He received the best paper award at IEEE VLSI Test Symposium 2000, top 10 papers at IEEE International Test Conference 2000 and the best panel at the IEEE VLSI Test Symposium 99. Intel awards include an Intel Achievement Award (2006), five Divisional Recognition Award (2000, 2002, and 2004), Technical Recognition Award (2002), Excellence Award (2001), Discover Award (2000), best papers at Intel Design and Test Technology Conference (2002, 2003). He has presented a tutorial on diagnosis and debug at the IEEE VLSI Test Symposium 2006, 2004 and 2003, IEEE International Test Conference 2004, Design Automation and Test in Europe 2004, European Test Symposium 2006, VLSI Design Conference 2006 and International Symposium on Testing and Failure Analysis 2003, 2004 and 2005. He is a member of IEEE, IEEE Computer Society and ACM.

Dr. Nagesh Tamarapalli is a Fellow with AMD India Design Center in Bangalore, India, where he is engaged in DFT and manufacturing test development for the next generation low-power Accelerated Processing Units (APUs). Prior to AMD, he was with Mentor Graphics DFT group where he worked on logic BIST, test compression and diagnosis tools. He has published in leading test conferences such as International Test Conference, Asian Test Symposium and journals such IEEE Transactions on CAD. A paper he co-authored at International Test Conference 1999 on logic BIST has been selected for Honorable Mention Award. This and another paper he co-authored at International Test Conference have been selected for “significant papers from the past 35 years”. He is the co-inventor of 14 approved US patents in the area of testing. He has delivered DFT seminars in India and USA at several venues including VLSI Design conference 2006, ISQED 2007 and DAC 2008. He holds MS in Electrical Engineering from Indian Institute of Technology, Kharagpur, India and PhD in Electrical Engineering from McGill University, Montreal, Canada.

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Session T4: Intellectual Property Protection and Security in System on a Chip

Susmita Sur-Kolay (Indian Statistical Institute, India)
Swarup Bhunia (Case Western Reserve University, Cleveland, USA)

7th January 2012 (9AM - 5PM)

Gigascale integration in recent semiconductor technology mandates design reuse in order to meet the design specifications in time. Electronic description of VLSI design being an intellectual property (IP), may be infringed upon during design reuse. This calls for incorporating techniques for intellectual property protection in the VLSI design flow. The IP of VLSI design, which culminates in fabrication of the integrated circuit, differs from other sources of IPs because in addition to its physical and structural description, it has also a behavioral specification which should remain unaltered after application of IP protection techniques. Security in activation of chips, especially in embedded systems, is an equally grave issue and has led to the paradigm of design-for-security.

This tutorial aims at presenting the major concerns related to IP security that are significant to both the circuit designers and developers of CAD tools. The nature of threats are broadly categorized as (i) misappropriation by hacking during electronic commerce and intentional reselling mostly at design level, and (ii) unauthorized design retrieval. Various attack models and the mechanisms for effective counter measures such as encryption, obfuscation, watermarking and fingerprinting, and certain analytic methods derived from the behavioral aspect, specific to chip designs, will be discussed. First, the scenario of digital rights management, attack models and security goals will be described. Next, the existing approaches for protection of soft IPs such as HDL codes, firm IPs especially at the value-added layout level, and hard IPs including DFM-enhanced layout will be presented. This will include a number of published research results by the presenters. Finally, the recent advances in tackling security issues for design of smart cards and cryptoprocessors will be surveyed.

Speaker Bios

Prof. Susmita Sur-Kolay received the B.Tech degree from Indian Institute of Technology, Kharagpur and the Ph.D. from Jadavpur University, India. She was a research assistant at Massachusetts Institute of Technology, post-doctoral fellow at University of Nebraska-Lincoln, and visiting faculty at Intel Corp., USA. She is presently a Professor in the Advanced Computing and Microelectronics Unit of the Indian Statistical Institute, Kolkata, India. Her research publications in peer-reviewed journals and premier conferences, and a book chapter, are in the areas of algorithmic CAD for VLSI physical design, fault modeling and testing, and IP protection of VLSI design. She has served in several program committees and editorial boards. She is a Distinguished Visitor of IEEE Computer Society (India), Senior Member of IEEE, Member of IET and VLSI Society of India. Among many other awards, she was the recipient of the President of India Gold Medal (summa cum laude) at IIT Kharagpur, and IBM Faculty Award. Dr. Sur-Kolay has presented a number of tutorials on physical design, and intellectual property protection (CASCOM 2009, ICED 2008, VLSI Design 2004). Web: http://www.isical.ac.in/~ssk/

Prof. Swarup Bhunia received his B.E. (Hons.) from Jadavpur University, Kolkata, India, and the M.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur. He received his Ph.D. from Purdue University, IN, USA, in 2005. Currently, Dr. Bhunia is an assistant professor of Electrical Eng. and Computer Sc. at Case Western Reserve University, USA. He has over ten years of research and development experience with over 120 publications in peer-reviewed journals and premier conferences. His research interests include low power and robust design, hardware security and protection, and novel test methodologies. Dr. Bhunia has given a number of tutorials on nanometer design issues in premier conferences (VTS 2010, ITC 2009, DATE 2009, ISLPED 2008). He is a senior member of IEEE. Web: http://vorlon.case.edu/~skb21/swarupbio.html

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Session T5: Advanced Analog-Mixed Signal System and Circuit Techniques

Pavan Hanumolu (Oregon State University, USA)
Un-Ku Moon (Oregon State University, USA)
Terri Fiez (Oregon State University, USA)

8th January 2012 (9AM - 5PM)

This tutorial begins with a broad overview of challenges in emerging mixed signal systems. After describing the system-level requirements along with the architecture and circuit needs, specific circuit and system solutions will be discussed to highlight promising approaches. Design techniques for advanced analog- and mixed signal circuit blocks such as phase-locked loops and analog-to-digital converters will be covered in detail. Finally, the modeling and analysis of substrate noise coupling in mixed-signal integrated circuits is addressed.

Detailed program: This day long tutorial addresses both the system- and circuit-level aspects of emerging mixed-signal systems. Analysis and design techniques to implement analog to digital converters, phase-locked loops, and the impact of substrate noise on these circuits in large system-on-chips will be discussed. The tutorial is categorized into the following four categories.

1. Challenges in Emerging Mixed-Signal Systems and Applications: With the successful integration of systems-on-a-chip for a wide range of ubiquitous applications including cell phones and gaming devices, new applications for SOCs are arising that create unique challenges at the circuit and system level. In this talk several emerging applications for integrated mixed-signal systems will be highlighted including sensor networks, solar electronics, and tracking and monitoring devices. The system level requirements will be discussed along with the architecture and circuit needs. Specific circuit and system solutions will be discussed to highlight promising approaches to address both application and process challenges in the coming decade.

2. Phase-Locking Techniques for Frequency Synthesis: Phase-locked loops (PLLs) are essential building blocks in all digital, analog, and radiofrequency integrated circuits (ICs). The noise, power, and area of PLLs determine many of the key performance parameters in all such ICs. This tutorial describes the fundamental principles and concepts of PLL design. After reviewing the operation of a simple type-1 PLL and the characteristics of its building blocks, the operating and design principles of a charge-pump PLL will be discussed in detail. Phase noise analysis using a small-signal model will be described and noise-bandwidth-power tradeoffs will be presented. Existing and emerging techniques to alleviate these tradeoffs will be briefly discussed.

3. Digitally-Enhanced Phase-Locking Techniques: Implementing analog phase-locked loops (PLLs) in deep sub-micron processes pose many design challenges. In this talk we elucidate such challenges and address those using highly digital architectures. Implementation details of the building blocks in a digital PLL such as time-to-digital converters, digital loop filters, and digitally-controlled oscillators will be described. Digital PLL specific design issues such as limit cycles and the dither jitter caused by them will be discussed.

4. Advanced and Emerging ADCs: Many analog IC designers and students are drawn to ADCs. While some ADC realizations have had a lasting impact, examples including pipelined ADCs with digital redundancy, flash ADCs with folding and interpolation, and multi-bit delta-sigma modulators with dynamic element matching, there are many more recent, advanced and emerging ADC design techniques that are receiving much attention and also gaining momentum in some areas. Many of these ideas are showered with doubts and honest criticism. However, we may also be entering a new era where some of these developments would help resolve the toughest submicron scaling challenges that analog designers face today. This tutorial will summarize and ponder the impact of a few selective as well as random slices of these advanced and emerging ADC designs.

Speaker Bios

Prof. Pavan Kumar Hanumolu received the Ph.D. degree in electrical engineering from Oregon State University in 2006. Currently, he is an Assistant Professor in the School of Electrical Engineering and Computer Science at the same University. His research interests include high-speed I/O interfaces, digital techniques to compensate for analog circuit imperfections, time-based signal processing, and power-management circuits. Web: http://web.engr.oregonstate.edu/~hanumolu/

Prof. Un-Ku Moon has been with the Oregon State University since 1998. Prior to that, he was with Bell Labs (Reading & Allentown) 1988-1989 and 1994-1998. He received a bachelor's degree from the University of Washington, a master's degree from Cornell University, and a Ph.D. from the University of Illinois, Urbana-Champaign. His current research activities are found at http://eecs.oregonstate.edu/~moon/research .

Prof. Terri S. Fiez is Professor and Head of Electrical Engineering and Computer Science at Oregon State University. From 2008 until mid 2009 she co-founded and served as CEO of Azuray Technologies, a startup developing micro-inverters for solar applications. Since returning to OSU in September 2009, she has taken on a leadership role for OSU's Sustainable Energy and Infrastructure (SENERGI) research thrust. After receiving her Ph.D. from OSU in 1990 she was a faculty member at Washington State University before returning to OSU to lead the department in 1999. She is an IEEE Fellow and her research interests are in analog and mixed-signal IC design and innovative engineering education approaches. Web: http://eecs.oregonstate.edu/people/fiez

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Session T6: Variability-resistant Software and Hardware for Nano-Scale Computing

Nikil Dutt (UC Irvine, USA)
Mani Srivastava (University of California, Los Angeles, USA)
Rajesh Gupta (University of California, San Diego, USA)
Subhashish Mitra (Stanford University, USA)

8th January 2012 (9AM - 5PM)

As semiconductor manufacturers build ever smaller components, circuits and chips at the nano scale become less reliable and more expensive to produce – no longer behaving like precisely chiseled machines with tight tolerances. Modern computing tends to ignore the variability in behavior of underlying system components from device to device, their wear-out over time, or the environment in which the computing system is placed. This makes them expensive, fragile and vulnerable to even the smallest changes in the environment or component failures. This tutorial presents an approach to tame and exploit variability through a strategy where system components -- led by proactive software -- routinely monitor, predict and adapt to the variability of manufactured systems. Unlike conventional system design where variability is hidden behind the conservative specifications of an “over-designed” hardware, we describe strategies that expose spatiotemporal variations in hardware to the highest layers of software. After presenting the background and positioning the new approach, the tutorial will proceed in a bottom-up fashion. Causes of variability at the circuit and hardware levels are first presented, and classical approaches to hide such variability are presented. The tutorial then presents a number of strategies at successively higher levels of abstraction – covering the circuit, microarchitecture, compiler, operating systems and software applications – to monitor, detect, adapt to, and exploit the exposed variability. Adaptable software will use online statistical modeling to learn and predict actual hardware characteristics, opportunistically adjust to variability, and proactively conform to a deliberately underdesigned hardware with relaxed design and manufacturing constraints. The resulting class of UnO (Underdesigned and Opportunistic) computing machines are adaptive but highly energy efficient. They will continue working while using components that vary in performance or grow less reliable over time and across technology generations. A fluid software-hardware interface will mitigate the variability of manufactured systems and make machines robust, reliable and responsive to changing operating conditions -- offering the best hope for perpetuating the fundamental gains in computing performance at lower cost of the past 40 years.

Speaker Bios

Prof. Nikil Dutt is a Chancellor's Professor of CS and EECS at the University of California, Irvine. He received a B.E.(Hons) from BITS Pilani in 1980, MS from Penn State in 1983 and PhD from the University of Illinois at Urbana-Champaign in 1989. His research interests are in embedded systems design automation, computer architecture, optimizing compilers, system specification techniques, distributed embedded systems, and brain-inspired architectures and computing. He has received numerous best paper awards and is coauthor of 7 books. Professor Dutt served as Editor-in-Chief of ACM Transactions on Design Automation of Electronic Systems (TODAES) (2003-2008) and currently serves as Associate Editor of ACM Transactions on Embedded Computer Systems (TECS) and of IEEE Transactions on VLSI Systems (IEEE-TVLSI). He was an ACM SIGDA Distinguished Lecturer during 2001-2002, and an IEEE Computer Society Distinguished Visitor for 2003-2005. He has served on the steering, organizing, and program committees of several premier CAD and Embedded System Design conferences and workshops, and serves or has served on the advisory boards of ACM SIGBED and ACM SIGDA. Professor Dutt is a Fellow of the IEEE, an ACM Distinguished Scientist, and recipient of the IFIP Silver Core Award. Web: http://www.ics.uci.edu/~dutt/

Prof. Rajesh Gupta is a professor and holder of the QUALCOMM endowed chair in Embedded Microsystems in the Department of Computer Science & Engineering at UC San Diego, California. He received his B. Tech. in Electrical Engineering from IIT Kanpur, India in 1984, MS in EECS from UC Berkeley in 1986 and a Ph. D. in Electrical Engineering from Stanford University in 1994. Earlier he worked as a circuit designer at Intel Corporation, Santa Clara, California as a member of three successful processor design teams; and on the Computer Science faculty at University of Illinois, Urbana-Champaign and UC Irvine. His current research is focused on energy efficient and mobile computing issues in embedded systems. He is author/co-author of over 150 articles on various aspects of embedded systems and design automation and four patents on PLL design, data-path synthesis and system-on-chip modeling. Professor Gupta serves as an advisor to Tallwood Venture Capital, RealIntent, Calypto and Packet Digital Corporation. Web: http://mesl.ucsd.edu/gupta/

Prof. Subhasish Mitra directs the Robust Systems Group in the Department of Electrical Engineering and the Department of Computer Science of Stanford University. Before joining Stanford, he was a Principal Engineer at Intel Corporation. Prof. Mitra’s research interests include robust system design, VLSI design, CAD, validation and test, and emerging nanotechnologies. His X-Compact technique for test compression has been used in more than 50 Intel products, and has influenced major CAD tools. The IFRA technology for post-silicon validation, created jointly with his student, was characterized as “a breakthrough” in the Communications of the ACM. His work on the first demonstration of imperfection-immune carbon nanotube VLSI circuits, jointly with his students and collaborators, was selected by NSF as a Research Highlight to the US Congress, and was highlighted as “a significant breakthrough” by the Semiconductor Research Corporation and the MIT Technology Review. Prof. Mitra’s major honors include the Presidential Early Career Award for Scientists and Engineers from the White House, the highest US honor for early-career outstanding scientists and engineers, ACM SIGDA Outstanding New Faculty Award, IEEE CAS/CEDA Pederson Award for the IEEE Transactions on CAD Best Paper, IEEE/ACM Design Automation Conference Best Paper Award, Intel Design and Test Technology Conference Best Paper Award, IBM Faculty Awards,Terman Fellowship, and the Intel Achievement Award, Intel’s highest corporate honor. At Stanford, he was honored multiple times by graduating seniors "for being important to them during their time at Stanford." Prof. Mitra also serves as an invited member on DARPA’s Information Science and Technology Board. Web: http://www.stanford.edu/~subh/

Prof. Mani Srivastava is on the faculty at UCLA where he is a Professor in the Electrical Engineering Department, and is also affiliated with the Computer Science Department and the Center for Embedded Networked Sensing. He received both the M.S. and Ph.D. degrees from the University of California, Berkeley, in 1987 and 1992, respectively. His graduate research was on silicon compilation, and hardware-software rapid prototyping and co-design of embedded VLSI systems for signal processing and control applications. Prior to joining the UCLA Electrical Engineering Department faculty in 1996, Srivastava worked on mobile and wireless multimedia networking at the Networked Computing Research Department at AT&T/Lucent Bell Labs at Murray Hill, NJ. At UCLA, Prof. Srivastava directs the Networked and Embedded Systems Laboratory (http://nesl.ee.ucla.edu), where his students work on diverse aspects of embedded and cyber-physical systems, distributed sensor networks, mobile computing, wireless networking, and pervasive communications. His research spans hardware, software, and algorithms, and emphasizes experimental systems and applications in domains such as mobile health, sustainability, participatory sensing, and defense. Srivastava has published extensively on his research with more than 240 papers many of which have been highly cited, holds five patents for his work on low-power and wireless networking, and has received many awards from top conferences. He is a Fellow of the IEEE, and has received the prestigious Okawa Foundation Grant, and the NSF CAREER Award. He has served as the EIC of the IEEE Trans. on Mobile Computing and the ACM Mobile Computing and Communications Review. Web: http://nesl.ee.ucla.edu/people/mbs/

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Session T7A:
New Modeling Methodologies for Thermal Analysis of 3D ICs and Advanced Cooling Technologies of the Future

Arvind Shridhar (EPFL, Switzerland)
David Atienza (EPFL, Switzerland)

8th Jsanuary 2012 (9AM - 5PM)

Increasing circuit densities, the proliferation of Multi-Processor Systems-on-Chips (MPSoCs) and high performance computing systems have resulted in an alarming rise in electronic heat dissipation levels, making the conventional thermal management strategies, including air cooled heat sinks, obsolete. The latest advancements in 3D Integration of IC dies have only aggravated this problem, creating a strong worldwide research interest in the development of advanced cooling technologies, such as interlayer microchannel liquid cooled heat sinks, to maintain ICs under safe operating temperatures. While this research has helped create a substantial amount of knowledge base pertaining to the heat transfer mechanism in advanced liquid cooling systems as applied to electronic circuits, this knowledge is yet to be transferred to the EDA community for it to be incorporated in the IC thermal simulators of the future. The existence of such tools becomes absolutely essential when IC designers are faced with the challenge of ascertaining the thermal reliability of their designs in the presence of liquid cooling systems. This tutorial aims to introduce the attendees to the key concepts that are needed to compute IC temperatures with and without microchannel liquid cooling and the principles behind compact modeling of forced convective heat transfer in advanced IC cooling technologies. A major part of this tutorial is based on the 3D- ‐ICE thermal simulator, which has been built by the Embedded Systems Laboratory in EPFL, Switzerland (URL: http://esl.epfl.ch/3D-­‐ICE ). This simulator is based on the Compact Transient Thermal Modeling for forced convective cooling advanced by our research group. Since its release in 2010, more than 50 research groups across the world have downloaded it and are actively using it for their research.

Speaker Bios

Prof. David Atienza received his MSc and PhD degrees in Computer Science and Engineering from Complutense University of Madrid (UCM), Spain, and Inter-University Micro-Electronics Center (IMEC), Belgium, in 2001 and 2005, respectively. Currently, he is Professor and Director of the Embedded Systems Laboratory (ESL) at EPFL, Switzerland, and Adjunct Professor at the Computer Architecture and Engineering Department of UCM. Additionally, he is Scientific Counselor of long-time research of IMEC Nederland (IMEC-NL), Holst Centre, Eindhoven, The Netherlands. His research interests focus on design methodologies for high-performance embedded systems and low-power Systems-on-Chip (SoC), including new thermal management techniques for 2D/3D Multi-Processor SoCs, wireless body sensor networks, dynamic memory management and memory hierarchy optimizations for embedded systems, novel architectures for logic and memories in forthcoming 3D nano-scale electronics, as well as Networks-on-Chip (NoC) design. In these fields, he is co-author of more than 150 publications in prestigious journals and international conferences. He has received a Best Paper Award at the IEEE/IFIP VLSI-SoC 2009 Conference and three Best Paper Award Nominations at the HPCS-WEHA 2010, ICCAD 2006 and DAC 2004 conferences. He is an Associate Editor of IEEE Transactions on CAD (in the area of System-Level Design), IEEE Letters on Embedded Systems and Elsevier Integration: The VLSI Journal. He is also an elected member of the Executive Committee of the IEEE Council of Electronic Design Automation (CEDA) since 2008 and an elected member of the Board of Governors of the IEEE Circuits and Systems Society (CASS) since 2010. Web: http://people.epfl.ch/david.atienza

Mr. Arvind Sridhar graduated with Bachelors in Electronics Engineering from Anna University, India in 2006 and with a Masters in Applied Science from the Department of Electronics, Carleton University, Canada in 2009, majoring in EDA. Since then, he has been working at the Embedded Systems Laboratory in EPFL, Switzerland as a doctoral researcher under the supervision of Dr. David Atienza. At EPFL, he developed the compact modeling methodology for forced convection in microchannels, which forms the basis for 3D-ICE, an open source thermal simulator which is currently being used by researchers in more than 50 research labs across the world. His research interests include Simulation and Optimization CAD for VLSI, Thermal Modeling and Computational Fluid Dynamics. Arvind Sridhar has handled courses in Circuit Theory, Signals and Systems and Electromagnetic Theory as a teaching assistant in Carleton University. In June 2011, he was one of the course instructors for the Microscale Heat Transfer course for doctoral students at EPFL, introducing the concept of compact modeling for microchannel liquid cooling of ICs and 3D-ICE. Web: http://people.epfl.ch/arvind.sridhar

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Session T7B: Optimally Addressing Verification Constraint Complexity for Effective Functional Convergence

Shankar Hemmady (Synopsys, USA)

8th January 2012 (2PM - 5PM)

As SoC design becomes larger and more complex, verification engineers are expanding constrained-random testing to meet the validation demand. This expansion creates a new set of challenges: engineers now face exponentially growing verification performance and capacity issues. It is no longer enough to write constraints that simply function to validate a design. Today, engineers must also optimize the constraints they write for performance if they wish to have any hope of both successfully validating their design and meeting their deadlines. In this tutorial, we discuss a scalable methodology for writing constraints and optimizing performance is which will improve engineers’ productivity to write and debug ever-increasing amounts of larger, more complex sets of constraints. Our goal is to reduce the time needed for functional convergence, and later for debug and volume manufacturing. We will also discuss the vital role of Verification IP providers and users in this scenario.

Speaker Bio

Mr. Shankar Hemmady is a Principal Engineer at Synopsys responsible for knowledge sharing and social networking. Over the past four years, Shankar was also responsible for power-aware verification, and verification planning and management solutions. He has managed the functional closure of over 25 commercial chips during the past 2 years as an engineering manager or consultant at 12 companies including AMD, Cirrus Logic, Fujitsu, Hewlett Packard, Intel, S3, Sun and Xerox. He has authored over 50 research papers and articles. In 2007, he authored the book, "Metric Driven Design Verification: An Engineer's and Executive's Guide to First Pass Success" which was named a best-seller at DAC 2007-08 by ESNUG and Springer Publications. Currently, Mr. Hemmady is currently serving as the Vice Chair of DVCon 2012 and as the Tutorials Chair of DesignCon 2012. He also serves on the Technical Program Committees of ISQED and IEDEC 2012.
Mr. Hemmady holds a B.S. in Electrical Engineering from the Indian Institute of Technology and an M.S. in Electrical & Computer Engineering from the University of Iowa. He completed Stanford's Advanced Management College executive program in 2002.

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Session T8A: Designing Silicon-Photonic Communication Networks for Manycore Systems

Ajay Joshi (Boston University, USA)

8th January 2012 (9AM – 12PM)

The goal of this tutorial is to explain the limits and opportunities of using silicon-photonic link technology for inter-chip and intra-chip communication in manycore systems. Silicon-photonic links have larger bandwidth density and lower energy than equivalent electrical links. In this tutorial, I will first provide an overview of the silicon-photonic device technology and link transceiver/tuning circuits. Using three silicon-photonic network case studies { on-chip tile-to-tile network, process-to-DRAM network and DRAM memory channel, the various silicon-photonic network design issues at the physical level, micro-architecture level and architecture level will be explained in detail. An iterative design process, where we move between these three levels to meet the power-performance specications under the silicon-photonic technology constraints will also be presented. At the end of the tutorial, attendees will have a broad understanding of the capabilities of silicon-photonic technology, and they will be able to design and analyze silicon-photonic networks for Manycore systems.

Speaker Bio

Dr. Ajay Joshi received M.S. and Ph.D. in Electrical and Computer Engineering from Georgia Institute of Technology in 2003 and 2006, respectively, and B.Engg. in Computer Engineering from University of Mumbai in 2001. He is currently an Assistant Professor in the Electrical and Computer Engineering department at Boston University. Prior to joining Boston University, he worked as a postdoctoral researcher in the Electrical Engineering and Computer Science department at Massachusetts Institute of Technology. His research interests span across various aspects of VLSI design including circuits and systems for communication and computation, and emerging device technologies including silicon photonics and carbon nanotubes. Web: http://people.bu.edu/joshi/Site/ICSG__People.html

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Session T8B: Wireless System Design and Systems Engineering Challenges

Ravi Kishore B (HCL, India)
Kameswara Rao B (HCL, India)
Muralidhar Reddy B (HCL, India)

8th January 2012 (2PM - 5PM)

Pervasiveness of wireless technology is impacting every aspect of the society and is becoming a de facto feature of any electronic product. This tutorial provides a comprehensive overview of wireless system design and brings out the systems engineering issues through real-life design case studies. It begins with an overview of a typical wireless system and the underlying RF technology. Next, a detailed view of wireless system design with mathematical underpinning of concepts and design of sub-systems will be presented; it highlights systems engineering issues in wireless product development. Subsequently, the tutorial presents the relevant system design case studies, for various wireless applications viz; medical electronics, consumer electronics, defense, telecommunications etc., and explains the methodologies to address the systems engineering issues. Finally, the tutorial explains the trends in future wireless systems design and the associated challenges. The last session concludes the tutorial, followed by a discussion.

Speaker Bios

Dr. B. Ravi Kishore is Associated General Manager at HCL Technologies Ltd., Chennai.  He had completed his Ph.D. from Tokyo Institute of Technology, Tokyo in the area of fault-tolerant computing and design for testability for asynchronous circuits, in March, 1998. He had worked with Texas Instruments (Japan) from 1998 to 2002 in design automation group for analog and mixed-signal design. He worked in the area of power analysis, design for manufacturability of mixed-signal circuits. Since 2003, he has been working with HCL Technologies, Chennai, India. From 2003 to 2006, he was responsible for the defining and implementing the system level reliability process for various high-integrity applications in medical, avionics and networking. He successfully initiated several large customer engagements in the areas of wireless infrastructure, consumer electronics, defense & security and headed the product development teams to build end-to-end solutions. Currently, he heads the Centre of Excellence (CoE) team for RF Systems Engineering since 2009. As a part of CoE activities, the team is responsible for new technology initiatives and developing wireless solutions for RF Systems Engineering, in the application areas of wireless infrastructure, consumer electronics, medical electronics, defense & security, industrial electronics etc.

Mr. Kameswara Rao B is Project Manager at HCL Technologies Limited, Chennai, India. He handles RF/wireless Projects and is responsible for design and delivery of RF and Microwave products / systems. He has had extensive experience of around 10 years in RF/Microwave Circuit & System Design across various domains like Wireless Infrastructure, Defense, Consumer Electronics and Industrial. He has a Bachelors Degree in Electronics and Communication Engineering from Institute of Engineers (India).

Mr. Muralidhar Bandi is Project Manager at HCL Technologies Limited, Chennai, India. He is responsible for developing complex wireless systems to address the Telecom and Defense market needs. He has worked on 2G/3G Base stations, multiband repeaters, optical wireless circuits to meet the Indoor & outdoor Distribution Antenna System requirements. Prior to the current assignment in HCL Technologies, he had worked with Bharat Electronics Limited on analog and digital television transmitters He has over 12 years of experience in RF and Microwave circuit designs and developing wireless transceivers for 2G/3G and 4G requirements. He had Bachelors in Technology Degree in Electronics and Communication Engineering from Nagarjuna University.

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