PAPER ID= 260

Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath

Sohan Purohit,

Marco Lanuzza,

Stefania Perri,

Pasquale Corsonello,

and Martin Margala,

Efficient Techniques for Directed Test Generation Using Incremental Satisfiability

Prabhat Mishra

and Mingsong Chen

PAPER ID= 93

A Novel Approach for Improving the Quality of Open Fault Diagnosis

Koji Yamazaki,

Toshiyuki Tsutsumi,

Hiroshi Takahashi,

Yoshinobu Higami,

Takashi Aikyo,

Yuzo Takamatsu,

Hiroyuki Yotsuyanagi,

and Masaki Hashizume

PAPER ID= 327

Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels

Weihuang Wang,

Gwan Choi,

and Kiran K. Gunnam,

Inline Assertions - Embedding Formal Properties in a Test Bench

Aritra Hazra,

Priyankar Ghosh,

Pallab Dasgupta,

and Partha Pratim Chakrabarti,

PAPER ID= 137

Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC

Hiroyuki Yotsuyanagi,

Masaki Hashizume,

Toshiyuki Tsutsumi,

Koji Yamazaki,

Takashi Aikyo,

Yoshinobu Higami,

Hiroshi Takahashi,

and Yuzo Takamatsu,

Environment and Process Adaptive Low Power Wireless Baseband Signal Processing Using Dual Real-Time Feedback

Muhammad Mudassar Nisar,

and Abhijit Chatterjee,

Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL

Vinod Viswanath,

Shobha Vasudevan,

and Jacob A. Abraham

Efficient Grouping of Fail Chips for Volume Yield Diagnostics

Lavanya Jagan,

Ratan Deep Singh,

V. Kamakoti,

and Ananta K. Majhi,

100KHz-20MHz Programmable Subthreshold G_m-C Low-Pass Filter
in 0.18μ-m CMOS

S. Ramasamy,

B. Venkataramani,

R. Niranjini,

and K. Suganya

Floorplanning for Partial Reconfiguration in FPGAs

Pritha Banerjee,

Megha Sangtani,

and Susmita Sur-Kolay

Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration

Tameesh Suri,

and Aneesh Aggarwal

A 20MS/s 5.6 mW 6b Asynchronous ADC in 0.6μm CMOS

Theja Tulabandhula,

and Yujendra Mitikiri,

PAPER ID= 298

Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits

Almitra Pradhan,

and Ranga Vemuri

Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips

Amir-Mohammad Rahmani,

Masoud Daneshtalab,

Ali Afzali-Kusha,

Saeed Safari,

and Masoud Pedram

Design of a Low Power, Variable-Resolution Flash ADC

Sreehari Veeramachanen,

A. Mahesh Kumar,

Venkat Tummala,

and M.B. Srinivas,

Efficient Analog/RF Layout Closure with Compaction Based Legalization

Subramanian Rajagopalan,

Sambuddha Bhattacharya,

and Shabbir H. Batterywala

Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis
of Network on Chips

Amir-Mohammad Rahmani,

Iman Kamali,

Pejman Lotfi-Kamran,

Ali Afzali-Kusha,

and Saeed Safari

Latency, Power and Performance Trade-Offs in Network-on-Chips
by Link Microarchitecture Exploration

Basavaraj Talwar,

Shailesh Kulkarni,

and Bharadwaj Amrutur

A Low Voltage CMOS Proportional-to-Absolute Temperature Current Reference

Sanjay Kumar Wadhwa

PAPER ID= 237

Reversible Logic Synthesis with Output Permutation

Robert Wille,

Daniel Große,

Gerhard W. Dueck,

and Rolf Drechsler

The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality

Irith Pomeranz,

and Sudhakar M. Reddy

Novel MOS Decoupling Capacitor Optimization Technique for Nanotechnologies

Bardia Bozorgzadeh,

and Ali Afzali-Kusha

Cone Resynthesis ECO Methodology for Multi-Million Gate Designs

Suresh Raman,

and Mike Lubyanitsky

PAPER ID= 116 S

New Techniques for Accelerating Small Delay ATPG and Generating
Compact Test Sets

Boxue Yin,

Dong Xiang,

and Zhen Chen

Switched-Capacitor Based Buck Converter Design Using Current Limiter
for Better Efficiency and Output Ripple

Tamal Das,

and Pradip Mandal

A General Approach to High-Level Energy and Performance Estimation in SoCs

Sandro Penolazzi,

Ahmed Hemani,

and Luca Bolognino

TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis

Alejandro Czutro,

Ilia Polian,

Matthew Lewis,

Piet Engelke,

Sudhakar M. Reddy,

and Bernd Becker

Exploiting Hybrid Analysis in Solving Electrical Networks

V. Siva Sankar,

H. Narayanan,

and Sachin B. Patkar

An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays

Kunal Ganeshpure,

and Sandip Kundu

Concept of "Crossover Point" and its Application on Threshold Voltage Definition
for Undoped-Body Transistors

Ratul Kumar Baruah,

and Santanu Mahapatra

Design, Implementation and Validation of an Open Source IP-PBX/VoIP Gateway SoC

Spyros Apostolacos,

George Lykakis,

Apostolos Meliones,

Vassilis Vlagoulis,

Emmanuel Touloupis,

and George Konstantoulakis

High-Speed On-Chip Event Counters for Embedded Systems

Nilanjan Mukherjee,

Artur Pogiel,

Janusz Rajski,

and Jerzy Tyszerg

Extended-Sakurai-Newton MOSFET Model for Ultra-Deep-Submicrometer CMOS Digital Design

Nishant Chandra,

Apoorva Kumar Yati,

and A.B. Bhattacharyya

Efficient Implementation of Floating-Point Reciprocator on FPGA

Manish Kumar Jaiswal,

and Nitin Chandrachoodan

A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios

T. Kempf,

S. Wallentowitz,

G. Ascheid,

R. Leupers,

and H. Meyr

Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate Stack

Abhisek Dixit,

Anirban Bandhyopadhyay,

Nadine Collaert,

Kristin De Meyer,

and Malgorzata Jurczak

ReConfigurable Technologies

Mona Mathur

Improved-Quality Real-Time Stereo Vision Processor

Sang-Kyo Han,

SeongHoon Woo,

Mun-Ho Jeong,

and Bum-Jae You"

A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection

Hidehiro Fujiwara,

Shunsuke Okumura,

Yusuke Iguchi,

Hiroki Noguchi,

Hiroshi Kawaguchi,

and Masahiko Yoshimoto

Encoding of Floorplans through Deterministic Perturbation

Debasri Saha,

and Susmita Sur-Kolay

Efficient Placement of Compressed Code for Parallel Decompression

Xiaoke Qin,

and Prabhat Mishra

A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital
True Random Number Generator in 45nm CMOS

Suresh Srinivasan,

Sanu Mathew,

Vasantha Erraguntla,

and Ram Krishnamurthy

Design Optimization and Automation for Secure Cryptographic Circuits

Kuan Jen Lin,

Yi Tang Chiu,

and Shan Chief Fang,

FPGA Based High Performance Double-Precision Matrix Multiplication

Vinay B.Y. Kumar,

Siddharth Joshi,

Sachin B. Patkar,

and H. Narayanan

Single Ended Static Random Access Memory for Low-Vdd, High-Speed
Embedded Systems

Jawar Singh,

Jimson Mathew,

Saraju P. Mohanty,

and Dhiraj K. Pradhan

A Novel Sustained Vector Technique for the Detection of Hardware Trojans

Mainak Banga,

and Michael S. Hsiao.

FPGA Implementation of Support Vector Machine Based Isolated Digit Recognition System

J. Manikandan,

B. Venkataramani,

and V. Avanthi

A "Stitch" in Time: Accurate Timekeeping with On-Chip Compensation

Prashant Bhargava,

and Mohit Arora

Systematic Methodology for High-Level Performance Modeling of Analog Systems

Soumya Pandit,

Chittaranjan Mandal,

and Amit Patra

Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression

Kimiyoshi Usami,

Toshiaki Shirai,

Tasunori Hashida,

Hiroki Masuda,

Seidai Takeda,

Mitsutaka Nakata,

Naomi Seki,

Hideharu Amano,

Mitaro Namiki,

Masashi Imai,

Masaaki Kondo,

and Hiroshi Nakamura,

Metric Based Multi-Timescale Control for Reducing Power in Embedded Systems

Nitin Kataria,

Forrest Brewer,

João Hespanha,

and Timothy Sherwood

A Comparison of Approaches to Carrier Generation for Zigbee Transceivers

Leburu Manojkumar,

Arun Mohan,

and Nagendra Krishnapura

A Method for the Multi-Net Multi-Pin Routing Problem with Layer Assignment

Tuhina Samantam,

Hafizur Rahaman,

Prasun Ghosal,

and Parthasarathi Dasgupta

Code Transformations for TLB Power Reduction

Reiley Jeyapaul,

Sandeep Marathe,

and Aviral Shrivastava

A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link

Vijay Khawshe,

Kapil Vyas,

Renu Rangnekar,

Prateek Goyal,

Vijay Krishna,

Kashinath Prabhu,

Pravin Kumar Venkatesan,

Leneesh Raghavan,

Rajkumar Palwai,

Thrivikraman M,

Kunal Desai,

and Abhijit Abhyankar,

A New Hardware Routing Accelerator for Multi-Terminal Nets

Kaleem Fatima,

and Rameshwar Rao

Simultaneous Peak Temperature and Average Power Minimization
during Behavioral Synthesis

Vyas Krishnan,

and Srinivas Katkoori

Simultaneous Routing and Feedthrough Algorithm to Decongest Top Channel

Shashank Prasad,

and Anuj Kumar

Low-Power Low-Voltage Analog Circuit Design Using Hierarchical Particle Swarm Optimization

Rajesh Amratlal Thakker,

M. Shojaei Baghini,

and Mahesh B. Patil

RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits

Koustav Bhattacharya,

and Nagarajan Ranganathan

Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs

V. Vireen,

N. Venugopalachary,

G. Seetharaman,

and B. Venkataramani

Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space

Shubhankar Basu,

Balaji Kommineni,

and Ranga Vemuri

Soft Error Rates with Inertial and Logical Masking

Fan Wang,

and Vishwani D. Agrawal

WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements

Chunhua Yao,

Kewal K. Saluja,

and Abhishek A. Sinkar

A Low Power Architecture to Extend the Tuning Range of a Quadrature Clock

Ramen Dutta,

and T.K. Bhattacharyya

Accelerating System-Level Design Tasks Using Commodity Graphics Hardware:
A Case Study

Unmesh Dutta Bordoloi,

and Samarjit Chakraborty

An Error Model to Study the Behavior of Transient Errors in Sequential Circuits

Karthikeyan Lingasubramanian,

and Sanjukta Bhanja

Fuzzy Logic Based Guidance to Graph Grammar Framework for Automated
Analog Circuit Design

Angan Das,

and Ranga Vemuri

Analysis of the Energy Quantization Effects on Single Electron Inverter Performance
through Noise Margin Modeling

Surya Shankar Dan,

and Santanu Mahapatra

An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations
Using Static Timing Analysis

Ramamurthy Vishweshwara,

Ramakrishnan Venkatraman,

Udayakumar H,

and Arvind N V

Exploring the Limits of Port Reduction in Centralized Register Files

Sandeep Sirsi,

and Aneesh Aggarwal

Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications

Sudeep Pasricha,

Nikil Dutt,

and Fadi J. Kurdahi

Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions

R. Venkatraman,

Shrikrishna Pundoor,

Arun Koithyar,

Madhusudan Rao,

and Jagdish C. Rao,

Temperature Aware Scheduling for Embedded Processors

Ramkumar Jayaseelan,

and Tulika Mitra

Impact of Bias Voltage on Magnetic Inductance of Carbon Nanotube Interconnects

K.C. Narasimhamurthy,

and Roy P. Paily

Coping with Variations through System Level Design

Nilanjan Banerjee,

Soumya Chandra,

Swaroop Ghosh,

Sujit Dey,

Anand Raghunathan,

Kaushik Roy

SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Weixun Wang,

Prabhat Mishra,

and Ann Gordon-Ross

Conservative QCA Gate (CQCA) for Designing Concurrently Testable
Molecular QCA Circuits

Himanshu Thapliyal,

and Nagarajan Ranganathan

H-NMRU: A Low Area, High Performance Cache Replacement Policy for Embedded Processors

Sourav Roy

Infrastructures for Education, Research and Industry in Microelectronics - A Look Worldwide and a Look at India

Bernard Courtois,

Kholdoun Torki,

Sophie Dumont,

Sylvaine Eyraud,

Jean-Francois Paillotin,

Gregory Di Pendina

Specification Driven Design of Phase Locked Loops

Prakash Easwaran,

Prasenjit Bhowmik,

and Rupak Ghayall

Unified Challenges in Nano-CMOS High-Level Synthesis

Saraju P. Mohanty,