Jaswinder S. Ahuja

J Viraraghavan



Dr. Janakiraman graduated with a PhD in VLSI in 2010 from the Indian Institute of Science, Bangalore. Later, he joined IBM Semiconductor Research and Development Center (SRDC) India where he worked on Embedded DRAM design for technology qualification in 14nm SOI technology. In the last couple of years he has been working on developing Embedded Non-Volatile Memory in standard logic processes and has led the India design team to a couple of test chips across 32nm, 22nm processes in SOI. He has been with GLOBALFOUNDRIES India since July 2015 as a Senior Member Technical Staff (SMTS) where his primary responsibility has been to lead the design activity of developing technology qualification vehicles for the Embedded NV memory on the GLOBALFOUNDRIES 14nm bulk process. His research interests include circuit design for memories and statistical analysis in VLSI. Today his talk will focus on the design aspects that are key to implementing a NV memory in a standard logic process using a Charge Trap Transistor.