SCHEDULE

BY INTERNATIONALLY ACCLAIMED SPEAKERS

The 30th International Conference on VLSI Design and 16th Embedded Design is a five day long conference which is going to be held at HICC from the 7th to 11th of January. The Tutorials will be held on the first two days which are the 7th and 8th. The main conference will be held over the next three days 9th, 10th and 11th

Day 1 – Saturday, January 7, 2017
8:00 AM – 9:00 AM Registrations
9:00 AM – 10:20 AM
10:20 AM – 10:50 AM BREAK
10:50 AM – 12:15 PM
SESSION T1 SESSION T3 SESSION T5
Santanu Chattopadhyay,
Rajit Karmakar
IIT-Kharagpur

Thermal Aware Testing of VLSI Circuits and Systems
More Info…

Preet Yadav,
Chi-Min Yuan,
NXP Semiconductor

The horizon from DRC to DFM (Design for Manufacturing): yield & reliability influence for sub-micron technology nodes
More Info…

Chandra Sekar,
Hemasunder,
Xilinx

Embedded C/C++ Xilinx SDSoC Development Environment
More Info…

12:15 PM – 1:15 PM Lunch break
1:15 PM – 3:30 PM
3:30 PM – 4:00 PM BREAK
4:00 PM – 5:30 PM
SESSION T2 SESSION T4 A SESSION T6
Aman Jain,
Seagate

Evolved Supply Set Based UPF Methodology
More Info…

Neel Gala,
Rahul Bodduna, Vinod Ganesan,
Arjun Menon,
V. Kamakoti,
Reconfigurable Intelligent Systems Engineering (RISE) Lab,
Department of Computer Science and Engineering, IIT Madras

High Level Modeling and Synthesis of Digital Systems.
More Info…

SESSION T4 B

Akshay Gupta,
Sayandeep Nag,
Sudheer Yadapalli,
Abhay Mandhaniya,
Qualcomm India

Low Power Design Architecture for Mobile & IOT devices

More Info…

Sujay Deb,
Sri Harsha Gade,
Hemanta Kumar Mondal,
IIIT Delhi

Communication Infrastructure for Future Exascale Processors
More Info…

Day 2 – Sunday, January 8, 2017
8:00 AM – 9:00 AM Registrations
9:00 AM – 10:30 AM
10:30 AM – 11:00 AM BREAK
11:00 AM – 12:30 PM
SESSION T7 SESSION T9 SESSION T11 SESSION T13
Jamie K Schaeffer,
Mahbub Rashed,
GLOBALFOUNDRIES

22FDX Technology for Connected and Low Power Systems
More Info…

Ayan Datta,
M. Ramakrishna,
Sarvesh Verma,
Saikrishna Joginapally,
Intel Technologies

Devices and Circuits to Address the challenges in IOT
More Info…

Mohammad Hasan,
Aligarh Muslim University,
Aligarh,
India.

Design of energy and area efficient circuits using Spin devices in combination with CMOS
More Info…

Nagarajan Viswanathan,
Srinivas Murthy,
Texas Instruments

Pushing the Envelope on Ultra High Speed SerDes Interfaces
More Info…

12:30 PM – 2:00 PM Lunch break
2:00 PM – 3:30 PM
3:30 PM – 4:00 PM BREAK
4:00 PM – 5:30 PM
SESSION T8 SESSION T10 SESSION T12 SESSION T14
John Barth,
Bipin Malhan,
INVECAS

Memory is Everywhere
More Info…

Kamalika Datta,
NIT Meghalaya,
Indranil Sengupta,
IIT Kharagpur

Memristors: technology, circuit models and applications
More Info…

Kalyan Bhattacharyya,
Amrita University,
Coimbatore

Design, Simulation, Fabrication and Testing of Microwave CMOS Distributed Oscillators, Amplifiers, Noise Cancelling LNA with Temperature Performances and Finally Design of 60 GHz 5G Receiver For Mobile Communication
More Info…

Paramesh Ramanathan,
University of Wisconsin,
Madison

Privacy Assurance in the IoT world
More Info…

Day 3 – Monday, January 9, 2017
7:30 AM – 8:30 AM Registrations
8:30 AM – 10:00 AM Inauguration
10:00 AM – 10:40 AM Keynote 1: Dr. V.K.Saraswat, Former Secretary of Defence (R & D), Former chief DRDO, Member, NITI AAYOG
10:40 AM – 11:00 AM Tea / Coffee break
11:00 AM – 11:40 AM Keynote 2: Sanjay Jha, CEO, Global Foundries
The Avatars of Intelligence – Rise of the IoT and the Cloud, More info…
11:40 AM – 12:20 PM Keynote 3: Walden C. Rhines, CEO, Mentor Graphics
Security: From Software to Silicon, More info…
12:20 PM – 1:20 PM Lunch Break
1:20 PM – 3:00 PM SESSION A1 SESSION B1 SESSION C1 SESSION D1 SESSION E1 SESSION F1 SESSION G1
Analog, Mixed Signal, and RF
Design – I

Caches and Memory

FPGA and Reconfigurable Systems

Low Power – I

PhD Forum

Student Conference

Industry Forum

A1.1
Sudipta Sarkar,
Yongda Cai,
University of Texas at Dallas

Two-Step Passive-Active Residue Transfer Technique for High-Speed Pipeline A/Ds

B1.1
Sukarn Agarwal,
Hemangee K.Kapoor,
IIT Guwahati

Towards a better lifetime for Non-volatile caches in chip multiprocessors

C1.1
Bibin Johnson,
Nimin Thomas,
Sheeba Rani J,
Indian Institute of Space Science and Technology,
College of Engineering Chengannur

An FPGA Based High Throughput Discrete Kalman Filter Architecture For Real-time Image Denoising

D1.1
Shounak Chakraborty,
Hemangee K. Kapoor,
IIT Guwahati

Towards Controlling Chip Temperature by Dynamic Cache Reconfiguration in Multiprocessors

To View Student Conference Agenda Click Here To View Indusry Forum Agenda Click Here
A1.2
Ashwin Kumar Siva Kumar,
Debasish Behera,
Nagendra Krishnapura,
IIT Madras

A Low Power Multi-Channel Input Delta-Sigma ADC Without Reset

B1.2
Debiprasanna Sahoo,
Manoranjan Satpathy,
Madhu Mutyam
IIT Bhubaneswar,
IIT Madras

An Experimental Study of Dynamic Bank Partitioning of DRAM in Chip Multiprocessors

C1.2
Sangeetha D,
Deepa P
Government College of Technology,
Coimbatore,
Tamilnadu

Efficient Scale Invariant Human Detection using Histogram of Oriented Gradients for IoT Services

D1.2
Anand Savanth,
Alex Weddell,
James Myers,
David Flynn,
Bashir Al-Hashimi,
ARM Ltd, University of Southampton

A 50nW Voltage Monitor Scheme for Minimum Energy Sensor Systems

To View Student Conference Agenda Click Here To View Indusry Forum Agenda Click Here
A1.3
Naveen Kadayinti,
Maryam Shojaei Baghini,
Dinesh Sharma,
IIT Bombay

A Clock Retiming Circuit for Repeaterless Low Swing On-Chip Interconnects

B1.3
Ishan Thakkar,
Sudeep Pasricha,
Colorado State University

DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency

C1.3
Manish Kumar Jaiswal,
Hayden So,
The University of Hong Kong

DSP48E Efficient Floating Point Multiplier Architectures on FPGA

D1.3
Hemanta Kumar Mondal,
Shashwat Kaushik,
Sri Harsha Gade,
Sujay Deb,
IIIT Delhi

Energy-efficient Transceiver for Wireless NoC

To View Student Conference Agenda Click Here To View Indusry Forum Agenda Click Here
A1.4
Javed GS,
Immanuel Raja,
Gaurab Banerjee,
Indian Institute of Science,
Bangalore

On-chip Non-intrusive Temperature Detection and Compensation of a Fully Integrated CMOS RF Power Amplifier

B1.4
Jiayin Li,
Kartik Mohanram,
University of Pittsburgh

Virtual Two-port Memory Architecture for Asymmetric Memory Technologies

C1.4
Manideepa Mukherjee,
Alexander Fell,
Apala Guha,
IIIT Delhi

DFGenTool: A Dataflow Graph Generation Tool for Coarse Grain Reconfigurable Architectures

D1.4
Shailesh Ghogalkar, Texas Instruments

(Invited Talk) Microcontrollers in Digital Power Markets: Challenges, Solutions, and Future Trends

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3:00 PM – 3:20 PM Tea / Coffee break
3:20 PM – 5:00 PM SESSION A2 SESSION B2 SESSION C2 SESSION D2 SESSION E2 SESSION F2 SESSION G2
Low Power – II

VLSI Architectures

Test, Reliability and Fault Tolerance – I

Security – I

PhD Forum

Student Conference

Industry Forum
A2.1
Sumit Naikwad,
Murali.K Rajendran,
Priya Sunil,
Ashudeb Dutta,
IIT Hyderabad

A Single Inductor, Single Input Dual Output (SIDO) Piezoelectric Energy Harvesting System

B2.1
Bidesh Chakraborty,
Mamata Dalui,
Biplab K Sikdar,
Haldia Institute of Technology,
NIT,
Durgapur, Indian Institute of Engineering Science and Technology Shibpur

Design of Coherence Verification Unit for Heterogeneous CMPs Integrating Update and Invalidate Protocols

C2.1
Pascal Raiola,
Dominik Erb,
Sudhakar Reddy,
Bernd Becker,
University of Freiburg,
University
of Iowa

Accurate Diagnosis of Interconnect Open Defects based on the Robust Enhanced Aggressor Victim Model

D2.1
Fatemeh Tehranipoor,
Nima Karimian,
Wei Yan,
John Chandy,
University of Connecticut

Study of Power Supply Variation as a Source of Random Noise

To View Student Conference Agenda Click Here To View Indusry Forum Agenda Click Here
A2.2
Saransh Sharma,
Avilash Mukherjee,
Abhishek Dongre,
Mrigank Sharad,
IIT Kharagpur

Ultra Low Power Sensor Node for Security Applications, Facilitated by Algorithm-Architecture Co-Design

B2.2
Noor Mahammad Sk,
Mohamed Asan Basiri M,
IIITDM, Kancheepuram,
IIT Kanpur

High Performance Integer DCT Architectures for HEVC

C2.2
Prasenjit Biswas,
Duncan. M.H. Walker,
Texas A&M University

Improved Path Recovery in Pseudo Functional Path Delay Test using Extended Value Algebra

D2.2
N. Nalla Anandakumar,
Mohammad Hashmi and Somitra,
Sanadhya,
SETS, Chennai,
IIIT Delhi

Compact Implementations of FPGA-Based PUFs with Enhanced Performance

To View Student Conference Agenda Click Here To View Indusry Forum Agenda Click Here
A2.3
Sukanta Dey,
Satyabrata Dash,
Sukumar Nandi,
Prof. Gaurav Trivedi,
IIT Guwahati

Markov Chain Model using Levy Flight for VLSI Power Grid Analysis

B2.3
Mohd Tasleem Khan,
Dr. Shaik Rafi Ahamed,
Prof. Forrest Brewer

Low Complexity and Critical Path based VLSI Architecture for LMS Adaptive Filter using Distributed Arithmetic

C2.3
Binod Kumar,
Ankit Jindal,
Virendra Singh,
Masahiro,
Fujita,
IIT Bombay,
University of Tokyo

A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation

D2.3
Darshana Jayasinghe,
Aleksandar Ignjatovic,
Sri Parameswaran,
University of New South Wales

NORA: Algorithmic Balancing without Pre-charge to Thwart Power Analysis Attacks

To View Student Conference Agenda Click Here To View Indusry Forum Agenda Click Here
5:00 PM – 6:00 PM Panel Discussion 1
“Feeding the Beast: Addressing the Computational Demands of Ubiquitous Analytics and Learning”

Manish Kothari, VP Engineering, Qualcomm
Prof. Anand Raghunathan, Purdue University
P.J. Narayanan, IIIT Hyderabad
Prakash Raghavendra, AMD

Day 4 – Tuesday, January 10, 2017
8:00 AM – 9:00 AM Registrations
9:00 AM – 9:45 AM Keynote 4: Venkat Mattela, CEO, REDPINE SIGNALS
The Internet of Things – Past, Present and the Future, More info…
9:45 AM – 10:30 AM Keynote 5: Jaswinder Ahuja, MD, CADENCE
The Sixth Force: Underlying shifts in silicon, computing, IoT and the cloud, More info…
10:30 AM – 10:50 AM Tea / Coffee break
10:50 AM – 12:30 PM SESSION A3 SESSION B3 SESSION C3 SESSION D3 SESSION E3 SESSION F3
Analog, Mixed Signal, and RF
Design – II

Embedded Systems

Formal Techniques in Design

Design Contest

Student Conference

WIE

A3.1
Abhishek Srivastava,
Nithin Sankar,
Devarshi Das,
Maryam Shojaei Baghini,
IIT Bombay

LNA-LO Co-Design Considerations For Low Intermediate Frequency Receivers In 401-406 MHz MedRadio Spectrum For Healthcare Applications

B3.1
Javed GS,
Gaurab Banerjee,
Indian Institute of Science,
Bangalore

High Gain Capacitance Sensor Interface for the Monitoring of Cell Volume Growth

C3.1
Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel,
Wolfgang,
Kunz,
University Of Kaiserslautern

Dynamic Power Optimization based on Formal Property Checking of Operations

To View Student Conference Agenda Click Here
Pamela Kumar, View Bio
Vice President,
Cloud Computing Innovation Council of India

Talk on “Cloud Computing & IoE – an India perspective”

A3.2
Deepak Joshi,
Satyabrata Dash,
Ayush Malhotra,
Pulimi Venkata Sai,
Rahul Das,
Dikshit Sharma,
Prof. Gaurav Trivedi,
IIT Guwahati,
Motilal Nehru National Institute of Technology Allahabad,
NIT Tiruchirappalli,
IIT(BHU), Varanasi,
Manipal Institute of Technology

Optimization of 2.4 GHz CMOS Low Noise Amplifier using Hybrid Particle Swarm Optimization with Levy Flight

B3.2
Kajal Varma,
geeta patil,
Biju,
Raveendran
BITS Pilani

DTLB: Deterministic TLB for Tightly Bound Hard Real-time Systems

C3.2
Antonio Bruto da Costa,
Pallab Dasgupta,
IIT Kharagpur

Generating AMS Behavioral Models with Formal Guarantees on Feature Accuracy

To View Student Conference Agenda Click Here
Sailasree Natarajan,
View Bio
India Site Leader,
Director Technology & Development,
GLOBALFOUNDRIES

Talk on “Evolution of Semiconductor Industry”

A3.3
Chandra Nyshadham and Krishna,
Kanth Gowri Avalur,
AMS Semiconductors India Pvt. Ltd.

A 6V to 42V High Voltage CMOS Bandgap Reference robust to RF interference for automotive applications

B3.3
Rajesh Kedia,
Yoosuf K K,
Pappireddy Dedeepya,
Munib Fazal,
Chetan Arora,
M.Balakrishnan
IIT Delhi

MAVI: An Embedded Device to Assist Mobility of Visually Impaired

C3.3
Sudipa Mandal,
Antonio Bruto da Costa, Aritra Hazra,
Pallab Dasgupta,
Bhushan Naware, Rama Mohan Chunduri,
Sanjib Basu
IIT Kharagpur,
IIT Madras,
Intel Technology India Pvt Ltd

Formal Verification of Power Management Logic with Mixed-Signal Domains

To View Student Conference Agenda Click Here
Deepti Sharma, View Bio
Manager,
GLOBALFOUNDRIES

Talk on “What next after Silicon ?”

A3.4
Mahesh Zanwar,
Subhajit Sen,
IIIT Bangalore

Programmable Output Multiphase Switched Capacitor Step-up DC-DC Converter with SAR-based Regulation

B3.4
Anshuman Tripathi,
Arnab Sarkar,
Partha Pratim Chakrabarti
IIT Guwahati,
IIT Kharagpur

Migration Aware Low Overhead ERfair Scheduler

C3.4
Antara Ain,
Akshay Mambakam,
Pallab Dasgupta,
Siddhartha Mukhopadhyay,
IIT Kharagpur

Feature Based Identification of Transmission Line Faults by Synchronous Monitoring of PMUs

To View Student Conference Agenda Click Here
Vaishali Neotia, View Bio
CEO and Co-Founder of Merxius

Exploring the buzz around Augmented and Virtual Reality

12:30 PM – 1:30 PM Lunch break
1:30 PM – 2:15 PM Plenary Talk 1 : Dr. Pulipati Madhav, CEO, Photonics Valley Corporation, Government of Telangana
Photonics Project for computing transformation, More info…
2:15 PM – 4:00 PM SESSION A4 SESSION B4 SESSION C4 SESSION D4 SESSION E4 SESSION F4
Analog, Mixed Signal, and RF
Design – III

Emerging Technologies – I

Digital Circuits

Design Contest

Student Conference

WIE

A4.1
Manikandan RR,
Venakat Narayana Rao,
IISc, Global Foundries

A High Performance Switchable Multiband Inductor Structure for LC-VCOs

B4.1
Debjyoti Bhattacharjee,
Farhad Merchant,
Anupam Chattopadhyay,
Nanyang Technological University

10nm FinFET. Efficient In-Memory computation of Binary BLAS on ReRAM Crossbar Arrays

C4.1
Satyajit Mohapatra,
Hari Shanker Gupta,
Jatindeep Singh,
Nihar Ranjan Mohapatra

A 64b/66b Line Encoding for High Speed Serializers

To View Student Conference Agenda Click Here
Mentoring & Networking workshop,
Seru Srinivas,
Deepti Sharma,
Sailasree Natarajan,
GLOBALFOUNDRIES
A4.2
Sanjay Wadhwa, Nidhi Chaudhry,
Design Manager, NXP

High accuracy, multi-output bandgap reference circuit in 16nm FinFet

B4.2
Bhuvaneshwari Y V,
Abhinav Kranti,
Indian Institute of Technology,
Indore

Extraction and Analysis of Mobility in Junctionless Double Gate

C4.2
Mitesh Limachia,
Pathik Viramgama,
Dr. Rajesh Thakker,
Dr. Nikhil Kothari,
Dharmsinh Desai University Nadiad,
VGEC Gandhinagar

Characterization of a Novel 10T Low-Voltage SRAM Cell With High Read and Write Margin

To View Student Conference Agenda Click Here
Mentoring & Networking workshop,
Seru Srinivas,
Deepti Sharma,
Sailasree Natarajan,
GLOBALFOUNDRIES
A4.3
Karthikeyan Shanmugavelu,
Ravi Kishore Bhagavatula,
HCL Technologies Limited

A Novel Design of Compact Broadband Microstrip Directional Coupler with High Directivity

B4.3
Abhoy Kole,
Kamalika Datta,
B. P. Poddar Institute of Management & Technology,
NIT Meghalaya

Improved NCV Gate Realization of Arbitrary Size Toffoli Gates

C4.3
Poorvi Jain,
Bishnu Prasad Das,
IIT Roorkee

Within-Die Threshold Voltage Variability Estimation Using Reconfigurable Ring Oscillator

To View Student Conference Agenda Click Here
Mentoring & Networking workshop,
Seru Srinivas,
Deepti Sharma,
Sailasree Natarajan,
GLOBALFOUNDRIES
A4.4
Vinay kumar,
Nikhil Puri,
Sudhir Kumar,
Sumit Srivastav,
Synopsys

A Sub-0.5V Reliability Aware-Negative Bitline write-assisted 8T DP-SRAM and WL strapping novel architecture to counter dual patterning issues in 10nm FinFET

B4.4
Vipul Mishra,
Himanshu Thaplital,
Bennett University,
University of Kentucky

Heuristic based Majority/minority Logic Synthesis for Emerging Technologies

C4.4
Mahadev Shirwaikar,
Naveen Kadayinti,
Dinesh Sharma,
IIT Bombay

Clock Skew Measurement using an All-Digital Sigma-Delta Time to Digital Converter

To View Student Conference Agenda Click Here Panel discussion
Startups in the Cloud Computing & IoE space

Dr. Vibha Tripathi , Founder Swajal
Arvind Ravulavaru, Founder, IOTSuitcase
Muralidhar Somisetty, CTO Innohabit
Abhay Egoor, Founder Thybolt

4:00 PM – 4:25 PM Tea / Coffee break
4:25 PM – 5:30 PM Tribute Talk : Vishwani.D.Agarwal & Prof. Jacob Abraham
Tribute to Prof. Edward, More info…
5:30 PM Awards Ceremony followed by Cultural Program and Banquet Dinner

Day 5 – Wednesday, January 11, 2017

8:00 AM – 9:00 AM Registrations
9:00 AM – 9:45 AM Keynote 6: Jennifer Wong, VP FPGA Design, XILINX
Package-Level HBM Integration: Technology Trends, Challenges and Applications, More info…
9:45 AM – 10:30 AM Keynote 7: Rajesh Banginwar, Principal Engineer, Internet of Things Group, INTEL
10:30 AM – 10:50 AM Tea / Coffee break
10:50 AM – 12:30 PM SESSION A5 SESSION B5 SESSION C5 SESSION D5
Analog, Mixed Signal, and RF Design – IV

Emerging Technologies – II

CMOS Technologies – I

User/Designer Track

RASDAT
A5.1
Anjali Gopinath,
Ravi Kumar Adusumalli,
Veeresh Babu Vulligaddala,
Srinivas M.B,
AMS Semiconductors India Pvt.Ltd,
Bits Pilani,
Hyderabad

A Switched-Capacitor Amplifier with True Rail-to-Rail Input Range Without Using a Rail-to-Rail Op-amp

B5.1
Sarit Chakrabortym
Susanta Chakraborty,
Indian Institute of Engineering Science and Technology,
Shibpur

A NOVEL APPROACH TOWARDS BIOCHEMICAL SYNTHESIS ON CYBERPHYSICAL DIGITAL MICROFLUIDIC BIOCHIP

C5.1
Avirup Dasgupta,
Chetan Gupta,
Anupam Dutta,
Yen-Kai Lin,
Srikanth Srihari,
Tamilmani Ethirajan,
Chenming Hu,
Yogesh Singh Chauhan
IIT Kanpur,
GlobalFoundries Engineering Private Limited,
University of California Berkeley

Modeling of Body-bias Dependence of Overlap Capacitances in Bulk MOSFETs

RASDAT
A5.2
Bhupendra Reniwal,
Pooran Singh,
Vikas Vijayvargiya,
santosh vishvakarma,
Indian Institute of Technology,
Indore

New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy-Efficient SRAM

B5.2
Bhawani Shankar,
Mayank Shrivastava,
Indian Institute of Science

ESD Behavior of AlGaN/GaN HEMT on Si: Physical Insights, Design Aspects, Cumulative Degradation and Failure Analysis

C5.2
Rajat Vishnoi,
Pratyush Pandey,
Mamidala Jagadesh Kumar,
Global Foundries,
University of Notre Dame,
IIT Delhi,
Jawaharlal Nehru University

GDC Drain Current Model for Tunnel FETs Considering Source and Drain Depletion Regions

RASDAT
A5.3
Venkatesh Mani Tripathi,
Sandeep Mishra,
Jyotishman Saikia,
Anup Dandapat,
IIT Patna,
NIT, Meghalaya,
KIIT University

A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access

B5.3
Madhav Rao,
IIIT Bangalore

Electrical modeling and characterization of copper/carbon nanotubes in tapered through silicon vias

C5.3
Milova Paul,
Christian Russ,
B Sampath Kumar,
Harald Gossner,
Mayank Shrivastava,
Indian Institute of Science,
Intel Neubiberg

Physics of Current Filamentation in ggNMOS Revisited: Was Our Understanding Scientifically Complete ?

RASDAT
A5.4
Mohammed Umar Shaikh,
Sivaramakrishna Rudrapati,
Nandish Bharat Thaker,
Shalabh Gupta,
IIT Bombay

Frequency Enhancement in Miller Divider with Injection-locking Portrait

B5.4
Debasri Saha,
Susmita Sur-Kolay,
A.K. Choudhury
School of IT,
University of Calcutta,
Indian Statistical Institute

Multi-objective optimization of placement and assignment of TSVs in 3D ICs

RASDAT
12:30 PM – 1:30 PM Lunch break
1:30 PM – 3:10 PM SESSION A6 SESSION B6 SESSION C6 SESSION D6
A6 – Test, Reliability and Fault Tolerance –
II

B6 – Security – II

C6 – CMOS Technologies – II

User/Designer Track

RASDAT
A6.1
Nihar Hage,
Rohini Gulve,
Masahiro Fujita,
Virendra Singh,
IIT Bombay,
University of Tokyo

On Testing of Superscalar Processors in Functional Mode for Delay Faults

B6.1
Krishnendu Guha,
Debasri Saha,
Amlan Chakrabarti,
University of Calcutta

Self Aware SoC Security to counteract Delay inducing Hardware Trojans at Runtime

C6.1
Adil Meersha,
Sathyajit B,
Mayank Shrivastava,
Indian Institute of Science, IISc, Indian Institute of Science

A Systematic Study on the Hysteresis Behaviour and Reliability of MoS2 FET

RASDAT
A6.2
Barry Muldrey,
Sabyasachi Deyati,
Abhijit Chatterjee,
Georgia Institute of Technology

Automatic Characterization of RF Device Nonidealities Via Iterative Learning Experiments on Hardware

B6.2
Anuroop K.B,
Anu James,
Neema M,
Adi Shankara Institute of Engineering And Technology,
Kalady,
Kerala

Hardware/Software Codesign For A Hybrid Substitution Box

C6.2
Manish Gupta,
Abhinav Kranti,
IIT Indore

Suppressing Single Transistor Latch Effect in Energy Efficient Steep Switching Junctionless MOSFETs

RASDAT
A6.3
Sparsh Mittal,
Haonan Wang,
Adwait Jog,
Jeffrey Vetter,
Oak Ridge National Laboratory,
College of William & Mary

Design and Analysis of Soft-Error Resilience Mechanisms for GPU Register File

B6.3
Rajit Karmakar,
N Prasad,
Santanu Chattopadhyay,
Rohit Kapur,
Indranil Sengupta,
IIT Kharagpur,
Synopsys

New Logic Encryption Strategy Ensuring Key Interdependency

C6.3
Pardeep Kumar,
Srivatsa S,
Priyanka Mantripragada,
Seema Upreti,
Shravya K V,
GlobalFoundries Engg. India Pvt. Ltd

Hybrid OPC Technique for Fast and Accurate Lithography Simulation

RASDAT
3:10 PM – 3:30 PM Tea / Coffee break